Controlled bias current buffer and method thereof

A method of controlling output drive current in a buffer circuit comprising:

• receiving an input signal at a first operational amplifier;
• providing a first boost current in response to detecting a transition of signal value of the input signal;
• coupling a second operational amplifier to the first operational amplifier, the second operational amplifier detecting the transition of the signal value of the input signal after receiving the first boost current and increasing output drive current capability of the second operational amplifier in response to the first boost current;
• detecting the transition of signal value of the input signal at the second operational amplifier and providing a second boost current within the second operational amplifier in response thereto;
• providing a buffered version of the transition of signal value of the input signal having an increased current drive;
• removing the first boost current when a first input of the first operational amplifier has a substantially same voltage potential as a second input thereof;
• and
• continuing to provide the buffered version of the transition of signal value of the input signal with an increased current drive until a first input of the second operational amplifier has a substantially same voltage potential as a second input thereof.

A circuit comprising:

• a first resistor having a first terminal for receiving an input signal and a second terminal;
• a first operational amplifier having a first input coupled to the second terminal of the first resistor, a second input coupled to a reference terminal for receiving a reference voltage substantially one-half of a predetermined power supply voltage potential, a signal output, and a current drive output, the current drive output providing a boost current in response to detecting a transition of signal value of the input signal and removing the boost current when the first input has a substantially same voltage potential as the second input;
• a second resistor having a first terminal coupled to the signal output of the first operational amplifier and a second terminal coupled to the first input of the first operational amplifier, the second resistor providing a feedback path for the first operational amplifier;
• a third resistor having a first terminal coupled to the signal output of the first operational amplifier and having a second terminal;
• a second operational amplifier having a first input coupled to the second terminal of the third resistor, a second input coupled to the reference terminal for receiving the reference voltage, a third input for receiving the boost current, and an output for providing an output voltage having an increased current drive during the transition of signal value of the input signal, the increased current drive being reduced to a smaller current drive during a time when the input signal has no signal transitions;
• and
• a fourth resistor having a first terminal coupled to the output of the second operational amplifier and a second terminal coupled to the first input of the second operational amplifier, the fourth resistor providing a feedback path for the second operational amplifier.