US 6,704,889 B2 · Enhanced embedded logic analyzer

Abstract

Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint. The EDA tool directs the logic analyzer to unload the data from its capture buffer for display on a computer. The breakpoint and sample number can be changed without recompiling. A JTAG port controls the logic analyzer. Inputs and outputs of the logic analyzer are routed to unbonded JTAG-enabled I/O cells. Alternatively, a user-implemented test data register provides a JTAG-like chain of logic elements through which control and output information is shifted. Stimulus cells provide control information to the logic analyzer, and sense cells retrieve data from the logic analyzer.

Claims18

Dependent claims

A programmable logic device (PLD) comprising:

PLD circuitry representing one iteration of an electronic design in a design process to create a final PLD;
a logic analyzer integrated within said PLD circuitry such that a portion of said PLD circuitry is connected to said logic analyzer;
a JTAG (Joint Test Action Group) port arranged to receive logic analyzer commands from outside said PLD;
and
a plurality of I/O cells arranged to receive command signals from said JTAG port and to provide said command signals to said logic analyzer.

2 more elements

Dependencies are inferred from the claim text.

Enhanced embedded logic analyzer

Life of this patent

Enhanced embedded logic analyzer

Life of this patent

Abstract

Claims18