Compact high-capacity switch

A switching unit, comprising:

• a plurality of receive port cards, each receive port card comprising at least one first M-way commutator, wherein the first M-way commutators over all the receive port cards range from a 1st first M-way commutator to an Nth first M-way commutator;
• a plurality of transmit port cards, each transmit port card comprising at least one second M-way commutator, wherein the second M-way commutators over all the transmit port cards range from a 1st second M-way commutator to an Nth second M-way commutator;
• a plurality of switch cards, each switch card comprising at least one first N-way commutator and a corresponding number of second N-way commutators, wherein the first N-way commutators over all the switch cards range from a 1st first N-way commutator to an Mth first N-way commutator and wherein the second N-way commutators over all the switch cards range from a 1st second N-way commutator to an Mth second N-way commutator, each switch card further comprising a time switch for controllably interchanging portions of signals present at the outputs of the at least one first N-way commutator on that switch card, and for providing switched signals to the inputs of the at least one second N-way commutator on that switch card;
• wherein the mth output of the nth first M-way commutator is connected to the nth input of the mth first N-way commutator and wherein the nth output of the mth second N-way commutator is connected to the mth input of the nth second M-way commutator, for 1<=m<=M and 1<=n<=N.

A port card, comprising:

• a connector for connecting the port card to a plurality of switch cards;
• at least one first M-way commutator and a corresponding number of second M-way commutators, the connector being connected to the outputs of the at least one first M-way commutator and to the inputs of the second M-way commutators, the first and second M-way commutators having a common commutation step rate controllable by a sequencing signal;
• and
• a sequencing unit connected to the connector and to the first and second M-way commutators, for generating the sequencing signal as a function of a clock signal received from the connector.

A circuit card, comprising:

• a connector distributed along an edge of the circuit card;
• a first commutator having a plurality of outputs connected to the connector;
• a second commutator having a plurality of inputs connected to the connector;
• wherein the first and second commutators cooperate with a plurality of other commutators and a distributed time switch to provide non-blocking time and space switching of signals at the inputs to the first commutator.

A switch card, comprising:

• a connector for connecting the switch card to a plurality of port cards;
• at least one first commutator and a corresponding number of second commutators, the connector being connected to the inputs of the at least one first commutator and to the outputs of the second commutators, the first and second commutators having a common commutation step rate controllable by a sequencing signal;
• means for controllably time switching a plurality of signals output by each first commutator and for providing a plurality of switched signals to the corresponding second commutator;
• and
• a sequencing unit connected to the connector and to the first and second commutators, for generating the sequencing signal as a function of a clock signal received from the connector.

A circuit card, comprising:

• a connector disposed along an edge of the circuit card;
• a first commutator having a plurality of inputs connected to the connector;
• a second commutator having a plurality of outputs connected to the connector;
• a time switch comprising a plurality of randomly addressable data memories connected between respective outputs of the first commutator and respective inputs of the second commutator;
• wherein the randomly addressable data memories are accessed according to a time-varying connection map;
• whereby the time switch cooperates with other time switches and the first and second commutators cooperate with other commutators to provide non-blocking time and space switching of a plurality of input signals.

A compound commutator, comprising:

• a plurality of M-way commutators distributed among a plurality of substantially parallel first circuit cards, wherein the M-way commutators over all the first circuit cards range from a 1st M-way commutator to an Nth M-way commutator, and wherein the M-way commutators have a common first commutation step rate;
• and
• a plurality of N-way commutators distributed among a plurality of substantially parallel second circuit cards, wherein the N-way commutators over all the second circuit cards range from a 1st N-way commutator to an Mth N-way commutator, and wherein the N-way commutators have a common second commutation step rate;
• wherein the mth output of the nth M-way commutator is connected to the nth input of the mth N-way commutator for all 1<=m<=M and 1<=n<=N;
• wherein the first and second commutation step rates are harmonically related;
• and
• wherein a normal to any first circuit card and a normal to any second circuit card are not parallel.