Power control system for synchronous memory device

A single chip memory device, comprising:

• a memory core;
• a read output pipeline operably coupled to the memory core, wherein the read output pipeline is operable to drive read data received from the memory core onto an external data bus;
• and
• a control circuit operably coupled to the read output pipeline, wherein the control circuit is operable to enable a clock signal to the read output pipeline in response to receipt of first control information over an external control bus, the first control information indicating a read operation;
• wherein the control circuit is configured to respond to the first control information and enable the clock signal prior to receipt of the read data by the read output pipeline.

A method for operation of a single chip memory device, comprising:

• receiving, over a control bus, first control information indicating a write operation;
• enabling a write clock signal to a receiver in response to receipt of the first control information;
• after enabling the write clock signal, receiving, by the receiver, over a data bus and using the write clock signal, write data corresponding to the write operation;
• and
• writing the write data to a memory core of the memory device.

A method for operation of a single chip memory device, comprising:

• receiving, over a control bus, first control information indicating a read operation from a memory core of the memory device;
• enabling a read clock signal to a read output pipeline in response to receipt of the first control information;
• and
• after enabling the read clock signal, outputting read data onto a data bus using the read clock signal and the read output pipeline;
• wherein the receiving, enabling and outputting are preformed within a single chip memory device.

A single chip memory device, comprising:

• a memory core;
• a receiver operably coupled to the memory core, wherein the receiver is operable to receive write data, over a data bus, corresponding to write operations to the memory core;
• and
• a control circuit operably coupled to the receiver, wherein the control circuit is operable to receive control information over a control bus, wherein the control circuit is operable to enable a clock signal to the receiver in response to receipt of the control information, wherein the control information indicates a write operation;
• wherein the control circuit is configured to respond to the control information and enable the clock signal prior to receipt of the write data by the receiver.