Double differential comparator and programmable analog block architecture using same
AssigneeLattice Semiconductor Corporation
InventorsJames L. Gorecki, Bill G. Gazeley, Yaohua Yang
Life of this patent
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Abstract
A double differential comparator can be efficiently implemented utilizing a first comparator stage having a folded cascode with floating gate input terminals and clamped single-ended output, and a capacitively coupled input stage for transferring a weighted sum of input signals to the floating gates of the first comparator stage. Additionally, the double differential comparator can be integrated into fully differential programmable analog integrated circuits. Such fully differential programmable analog integrated circuits can also include a differential output digital-to-analog converter to be used with or without the double differential comparator.
Claims26
A programmable analog integrated circuit for receiving a differential analog input signal and providing a processed differential analog output signal, the programmable analog circuit comprising:
- a first programmable analog circuit block, the first programmable analog circuit block having first analog circuit block positive and negative input terminals and first analog circuit block positive and negative output terminals;
- a double differential comparator, the double differential comparator including:
- first comparator positive and negative input terminals;
- second comparator positive and negative input terminals;
- and
- comparator positive and negative output terminals, the double differential comparator providing a logic high output signal at the comparator output terminals when a first differential voltage applied to the first comparator input terminals is positive with respect to a second differential voltage applied to the second comparator input terminals;
- and
- an analog routing pool, the analog routing pool controlling the routing of the differential analog input signal and signals provided by and to the first programmable analog circuit block and the double differential comparator, the analog routing pool being programmable.
A double differential comparator comprising:
- first and second MOSFETs coupled at their sources to form a differential pair;
- first comparator positive and negative input terminals, the first comparator positive input terminal coupled to the gate of the first MOSFET and the first comparator negative input terminal coupled to the gate of the second MOSFET;
- second comparator positive and negative input terminals, the second comparator positive input terminal coupled to the gate of the second MOSFET and the second comparator negative input terminal coupled to the gate of the first MOSFET;
- and
- comparator positive and negative output terminals,
- the double differential comparator providing a logic high output signal at the comparator output terminals when a first differential voltage applied to the first comparator input terminals is positive with respect to a second differential voltage applied to the second comparator input terminals.
A double differential comparator comprising:
- a differential input comparator having first and second floating gate input terminals;
- a capacitively coupled input stage coupled to the differential input comparator, the capacitively coupled input stage including first comparator positive and negative input terminals and second comparator positive and negative input terminals providing to the first and second floating gate input terminals a weighted sum of signals applied to the comparator input terminals;
- and
- comparator positive and negative output terminals,
- the double differential comparator providing a logic high output signal at the comparator output terminals when a first differential voltage applied to the first comparator input terminals is positive with respect to a second differential voltage applied to the second comparator input terminals.
Dependencies are inferred from the claim text.