Loading patent…
AssigneeMotorola, Inc.
InventorsJoseph J. Nahas, Thomas W. Andre, Bradley J. Garni
Estimating the term…
In a memory, a bias circuit (112, 212, 312, 412) uses a current reference (108) for providing a reference current and control circuitry (106, 120) to bias a sense amplifier (114) with a varying voltage (VB). The varying voltage maintains current through MRAM bit cells (177-179) at a value proportional to the reference current over variations in average bit cell resistance with immunity to variations in process, supply voltage and temperature. In one form, a mock sense amplifier (122, 126, 132, 134) and mock array of bit cells (130, 136) are used to establish internal steady state voltages equivalent to a steady state condition of the sense amplifier with equalized outputs and to generate the varying bias voltage. Matching diode-connected transistors in each of the control circuitry and either the mock sense amplifier or the sense amplifier is used to generate the varying bias voltage.
A sense amplifier bias circuit for a memory having a sense amplifier and an array of bit cells, each of the bit cells having at least two distinct resistance states, comprising:
A sense amplifier bias circuit for a memory having a sense amplifier and an array of bit cells, each of the bit cells having at least two distinct resistance states, comprising:
A sense amplifier bias circuit for a memory having a sense amplifier and an array of bit cells, each of the bit cells having at least two distinct resistance states, comprising:
A memory having a sense amplifier bias circuit, the memory comprising:
A memory having a sense amplifier bias circuit, the memory comprising:
Dependencies are inferred from the claim text.