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US 6,700,155 B1Granted
Charge trapping device and method for implementing a transistor having a configurable threshold
AssigneeProgressent Technologies, Inc.
InventorsTsu-Jae King, David K. Y. Liu
Life of this patent
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Abstract
A device and method uses charge trapping to configure and adjust a threshold voltage (Vt) for a field effect transistor (FET). The charge trapping mechanism can be controlled by bias voltages applied to the FET, so that rapid/dynamic changes can be made to Vt without the use of conventional program/erase cycles. The threshold voltage can thus be set as a function of applied operating voltages.
Claims22
A semiconductor structure comprising:
- a dielectric trapping layer located proximate to a transistor channel, which transistor channel is capable of carrying a current that varies from a first current value associated with a conducting condition for the transistor channel, to a second current value associated with a non-conducting condition for said transistor channel channel, said second current value being substantially less than said first current value;
- a plurality of carrier trapping sites within said dielectric layer, said carrier trapping sites being configured for trapping carriers that are electrically biased by an electrical control field to move from said channel into said dielectric layer;
- wherein said said trapping sites have a concentration and arrangement within said dielectric layer so that said current in said transistor channel can be varied between said first current value and said second current value by the action of said trapping sites adjusting said current in accordance with a value of said electrical control field.
A metal-insulator-semiconductor field-effect transistor (MISFET) comprising:
- first conductivity type doped source and drain regions formed in the surface of a semiconductor substrate and separated by a second conductivity type doped channel region,
- said second conductivity type being opposite to said first conductivity;
- a gate formed over and electrically insulated from said channel region by a gate dielectric;
- said gate dielectric including one or more charge trapping sites located near an interface with said second conductivity type channel region and which are configured to allow a transistor threshold voltage of the MISFET to be significantly altered in a dynamic and reversible manner by effectuating an adjustable charge trapping mechanism in response to an adjustable bias voltage applied to the MISFET wherein said adjustable bias voltage is not a program and/or an erase cycle.
1 more element
A method of operating a silicon based transistor device comprising the steps of:
- (a) receiving a bias signal across a channel region of the semiconductor device, said channel region being coupled to a source and a drain region;
- (b) receiving a gate control signal at a gate of the transistor device;
- and
- (c) configuring a dielectric layer located proximate to said gate to trap a number of carriers flowing in said channel sufficient to cause a change in a threshold voltage of the transistor device;
- wherein said number of carriers that are trapped in said dielectric layer and said change in said threshold voltage of the transistor device are controlled by adjusting said bias signal and without using a program and/or an erase cycle.
2 more elements
Dependencies are inferred from the claim text.