US 6,696,873 B2 · Single event upset hardened latch

Abstract

A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the keeper circuit of the first latch and is cross-coupled with the gates of the keeper circuit of the first latch. The latch is hardened against single event upsets and an arbitrary number of successive SEUs attacking a single node, provided that the time between successive SEUs is larger than the recovery time of the latch. An alternate embodiment of the hardened latch includes a split buffer output. This embodiment is capable of reducing the propagation of erroneous transients. Another alternate embodiment of the hardened latch includes a Miller C buffer output. This embodiment is capable of reducing the propagation of erroneous transients below the level achievable in a hardened latch employing a split buffer output.

Claims4

Dependent claims

A latch comprising:

a pair of clock inverters;
a first latch comprising a set of transistors, the first latch to couple directly to the pair of clock inverters;
a second latch comprising a second set of transistors, wherein the second set of transistors corresponds to the set of transistors in both number of transistors and types of transistors, the second latch to couple directly to the pair of clock inverters;
and
an output gate having more than one buffer to drive an output port coupled to an output of the first latch and an input of the second latch, wherein the output gate is a dual input node Miller C buffer.

2 more elements

Dependencies are inferred from the claim text.

Single event upset hardened latch

Life of this patent

Single event upset hardened latch

Life of this patent

Abstract

Claims4