Capturing and evaluating high speed data streams
AssigneeTeradyne, Inc.
InventorsAlan J. Reiss, Gordon B. Saksena
Life of this patent
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AssigneeTeradyne, Inc.
InventorsAlan J. Reiss, Gordon B. Saksena
Estimating the term…
A system and method for capturing and evaluating high-speed serial data streams using conventional component testers includes a high-speed latching comparator coupled to the output of a device under test (DUT). The component tester stimulates the DUT to produce a high-speed serial data stream and strobes the latching comparator at predetermined instants of time relative to the serial data stream. In response, the latching comparator samples the digital state of the serial data stream and holds the sampled state. The component tester reads and stores the held state. The tester samples the serial data stream at multiple locations in this fashion, and takes multiple samples at each location. The tester averages the samples acquired at each location to render a probability function of the serial data stream verses time. The probability function has values that vary between zero and one, corresponding to the average value of the digital readings sampled at each point. From the probability function, significant timing characteristics of the serial data stream can be deduced, for example, jitter, intersymbol interference, and eye closure.
A method for testing a device under test (DUT) that generates a serial data stream, comprising the steps of:
A method of programming a tester to capture a serial data stream from the output of a SerDes device, comprising:
The method as recited in step 12, further comprising adjusting the vector period determined in step A so each bit of the serial data stream lasts for an integer number of tester timing LSB's.
In an automatic test system, an apparatus for testing a device under test (DUT) that generates a serial output signal, comprising:
Dependencies are inferred from the claim text.