Flexible I/O subsystem architecture and associated test capability

A method of selectively transferring data signals between signal-producing elements and signal-receiving elements, comprising:

• providing a first data transfer mechanism that has a plurality of input ports and a plurality of output ports, each input port being connected to one of the signal-producing elements and each output port being connected to one of the signal-receiving elements;
• accepting a data signal from a first signal-producing element;
• accessing a look-up table, which is stored in a memory, to determine what should be done with the data signal;
• directing the data signal to at least one of the signal-receiving elements through at least one of the output ports according to information contained in the look-up table;
• wherein the first data transfer mechanism and the look-up table are connected to a data bus, the data bus being connected to a processor, the method further including sending data signals from the processor to an output port according to instructions contained in the look-up table;
• directing data signals from the processor to a first output port;
• connecting the first output port to a first input port;
• directing the data signals from the processor to one of the signal-receiving elements through another of the output ports according to information contained in the look-up table.

A method of selectively transferring data signals between signal-producing elements and signal-receiving elements, comprising:

• providing a first data transfer mechanism that has a plurality of input ports and a plurality of output ports, each input port being connected to one of the signal-producing elements and each output port being connected to one of the signal-receiving elements;
• accepting a data signal from a first signal-producing element;
• accessing a look-up table, which is stored in a memory, to determine what should be done with the data signal;
• directing the data signal to at least one of the signal-receiving elements through at least one of the output ports according to information contained in the look-up table;
• connecting one of the output ports with one of the input ports;
• defining a predetermined limit on the number of signal-receiving elements to which the data signal may be transferred in a transfer iteration;
• after accepting the data signal through one of the input ports, accessing the lookup table to determine the number of transfers that are required for the date signal;
• routing the transfers that do not exceed the predetermined limit to the signal-receiving elements as directed by the information contained in the look-up table;
• directing the transfers that exceed the predetermined limit through the output port that is connected to the input port;
• accessing the look-up table to determine where the transfers exceeding the predetermined limit are to be routed;
• and
• repeating the routing, directing and accessing steps until the data signal has been transferred to all desired signal-receiving elements.

An apparatus for transferring data signals, comprising:

• a first input/output (I/O) device having a first plurality of input ports attached to signal-producing elements and a first plurality of output ports attached to signal-receiving elements, the first I/O device being connected to a data bus that transfers data signals between all components connected thereto, wherein the data bus is connected to a processor, and wherein each data signal entering the first data transfer mechanism through the data bus and the first plurality of input ports has a data identification information associated therewith;
• a first memory connected to the data bus, the first memory storing at least one transfer directive that corresponds to each data identification information;
• a second memory connected to the data bus, the second memory storing data signals as instructed by the transfer directive;
• wherein the first I/O device directs data signals from at least one of the first plurality of input ports and at least one of the components connected to the data bus, to at least one of the first plurality of output ports and at least one of the components connected to the data bus, according to the at least one transfer directive stored in the first memory;
• a second I/O device connected to the data bus, the second I/O device having a second plurality of input ports attached to signal-producing elements, the second I/O device further having a second plurality of output ports attached to signal-receiving elements, wherein each data signal entering the second data transfer mechanism through the data bus and the second plurality of input ports has a data identification information associated therewith;
• wherein at least one transfer directive corresponding to each data identification information is stored in the first memory;
• and
• wherein the second I/O device directs data signals from at least one of the second plurality of input ports and at least one of the components connected to the data bus, to at least one of the second plurality of output ports and the components connected to the data bus, according to the at least one transfer directive stored in the first memory.