DDR II write data capture calibration
AssigneeMicron Technology, Inc.
InventorsWen Li, Christopher K. Morzano
Life of this patent
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Abstract
A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., “1100,” is sent on the data path. The digital circuit captures the data using a clock signal, examines the data signal for the predetermined pattern and adjusts a delay applied to the data signal until the predetermined pattern is recognized. Then the delay is further adjusted until the predetermined pattern is no longer recognized indicating that an edge of the eye of the data is near a clocking edge of the clocking signal. The delay applied to the data signal is then further adjusted by a predetermined amount to position the clock edge near the center of the data eye.
Claims66
A method of calibrating a data path of a digital circuit, said method comprising:
- clocking an input data signal on said data path into said digital circuit using a clock signal, each bit of said input data signal having a data eye during which said bit is valid;
- adjusting the relative timing of said input data signal with respect to said clock signal to position a clocking transition of said clock signal at an edge of said data eye;
- and
- further adjusting the relative timing of said input data signal with respect to said clock signal by moving the data signal relative to the clock signal by a predetermined amount which is approximately equal to one-half of a width of said data eye to position said clocking transition at approximately a center of said data eye.
A system for calibrating a data path of a digital circuit, said system comprising:
- a latch circuit for clocking an input data signal on said data path into said digital circuit using a clock signal, each bit of said input data signal having a data eye during which said bit is valid;
- a logic circuit for adjusting the relative timing of said input data signal with respect to said clock signal to position a transition of said clock signal at an edge of a data eye, said logic circuit further adjusting the relative timing of said input data signal with respect to said clock signal by moving the data signal relative to the clock signal by a predetermined amount which is approximately equal to one-half of a width of said data eye to position said clocking transition at approximately a center of said data eye.
An integrated circuit semiconductor device comprising a system for calibrating a data path of a digital circuit, said system comprising:
- a latch circuit for clocking an input data signal on said data path into said digital circuit using a clock signal, each bit of said input data signal having a data eye during which said bit is valid;
- a logic circuit for adjusting the relative timing of said input data signal with respect to said clock signal to position a transition of said clock signal at an edge of a data eye, said logic circuit further adjusting the relative timing of said input data signal with respect to said clock signal by moving the data signal relative to the clock signal by a predetermined amount which is approximately equal to one-half of a width of said data eye to position said clocking transition at approximately a center of said data eye.
A processor system comprising:
- a processor;
- and
- a dynamic random access memory (DRAM) coupled to said processor, at least one of said processor and memory having a system for calibrating a data path of a digital circuit, said system for calibrating comprising:
- a latch circuit for clocking an input data signal on said data path into said digital circuit using a clock signal, each bit of said input data signal having a data eye during which said bit is valid;
- a logic circuit for adjusting the relative timing of said input data signal with respect to said clock signal to position a transition of said clock signal at an edge of a data eye, said logic circuit further adjusting the relative timing of said input data signal with respect to said clock signal by moving the data signal relative to the clock signal by a predetermined amount which is approximately equal to one-half of a width of said data eye to position said clocking transition at approximately a center of said data eye.
Dependencies are inferred from the claim text.