Processor interfacing to memory-centric computing engine

A method of interfacing a processor bus to a computation engine having a microprogrammable memory-centric controller and an array of memory, the method comprising the steps of:

• providing a predetermined series of microcode instruction for execution by the MCC;
• selecting a start address within the series of microcode instruction for carrying out a corresponding operation;
• and
• executing the series of microcode instruction in the MCC beginning at the selected start address so as to carry out the corresponding operation in the engine;
• wherein said selecting step includes decoding an address asserted by the processor and said decoding step includes providing hare-wired decoding logic in the MCC arranged so that at least one selected address automatically decodes so as to initiate a predetermined operation.

A memory-centric computing engine for connection to an external processor bus to supplement operation of a CPU also coupled to the processor bus, the computing engine comprising:

• an array of DRAM memory on board the computing engine;
• an execution unit coupled to the DRAM array for executing selected operations on data stored in the DRAM array;
• a memory controller (MCC) for controlling and addressing the DRAM array;
• and
• a bus interface controller for interfacing the engine to the processor bus;
• and
• a buffer memory under control of the bus interface controller and coupled both to the processor bus and to the DRAM memory array for buffering data transfers between the DRAM memory array and the external processing bus;
• wherein the DRAM array includes an executing memory block and an I/O memory block, and the DRAM array is reconfigurable under control of the MCC for swapping said blocks of memory to reduce latency of data transfer operations;
• and
• wherein he I/O memory block comprises rows of memory cells, each row having a number of bit cells equal to an integer multiple of the buffer memory word size selected for bandwidth matching the buffer memory and the DRAM array.

A memory-centric computing engine for connection to an external processor bus to supplement operation of a CPU also coupled to the processor bus, the computing engine comprising:

• a bus interface controller (BIC) for interfacing the engine to the processor bus;
• an array of DRAM memory on board the computing engine, the DRAM memory including an I/O memory block and an execution memory block;
• an execution unit coupled directly to the execution memory block of the DRAM array for executing selected operations on data stored in the DRAM array;
• and
• a memory-centric controller for controlling and addressing the DRAM array;
• and
• a buffer memory under control of the bus interface controller and coupled both to the processor bus and to the I/O memory block of the DRAM memory array for buffering data transfers between the processor bus and the DRAM memory array so as to support execution in the execution unit concurrently with data transfer between the DRAM array and the buffer memory.

A method of interfacing a standard processor bus to a memory-centric computation engine attached to the processor bus, to carry out selected operations in the computation engine, the method comprising the steps of:

• on the standard processor bus, asserting a first predetermined address;
• in the computation engine, detecting the first predetermined address;
• in the computation engine, responsive to detecting the first predetermined address, loading microcode into the computation engine under control of a memory-centric controller (MCC) on board the computation engine;
• asserting a second predetermined address on the processor bus;
• in the computation engine, detecting the second predetermined address;
• in the computation engine, responsive to detecting the second predetermined address, initiating a selected engine library operation;
• asserting a third predetermined address on the processor bus;
• and
• in the computation engine, detecting the third predetermined address;
• in the computation engine, responsive to detecting the third predetermined address, initiating an I/O operation between the processor bus and the computation engine under control of the MCC to acquire data for the selected library operation;
• and
• then executing the selected library operation on the acquired data.

A method of interfacing a processor bus to a computation engine having a microprogrammable memory-centric controller (MCC) and an array of memory, the method comprising of:

• providing a predetermined series of microcode instructions for execution by the MCC;
• selecting a start address within the series of microcode instructions for carrying out a corresponding operation;
• and
• executing the series of microcode instructions in the MCC beginning at the selected start address so as to carry out the corresponding operation in the engine;
• wherein said selecting step includes decoding an address asserted by the processor and said decoding step includes microprogramming the MCC, including providing a lookup table so as to enable the MCC to translate the asserted address into the microcode start address.