Shift register and liquid crystal display using the same

An LCD comprising a display cell array circuit, a data driving circuit and a gate driving circuit formed on a transparent substrate, the display cell array circuit comprising multiple data lines and multiple gate lines, each of the display cell arrays connected to a corresponding pair of data line and gate line,

• the gate driving circuit comprising a shift register including multiple stages connected one after another to each other, the multiple stages having a first stage in which a start signal is coupled to an input terminal, for sequentially selecting the multiple gate lines using an output signal of each stage, and the multiple stages having odd stages for receiving a first clock signal, and even stages for receiving a second clock signal having a phase opposite to the first clock signal,
• wherein the each stage comprises:
• an input terminal connected to an output terminal of a previous stage;
• an output terminal connected to a corresponding gate line;
• a control terminal connected to an output terminal of a next stage;
• a clock terminal into which a corresponding clock signal is inputted;
• a pull-up means connected between the clock terminal and the output terminal, for pulling-up the corresponding gate line during a duty period of the clock signal of when the pull-up means is turned on;
• a pull-down means connected between the output terminal and a first power voltage, for pulling-down the corresponding gate line when the pull-down means is turned on;
• a pull-up driving means connected to an input node of the pull-up means, for turning on the pull-up means in response to a front edge of an input signal supplied to the input terminal and turning off the pull-up means in response to a front edge of a control signal supplied to the control terminal;
• a pull-down driving means connected to an input node of the pull-down means, for turning off the pull-down means in response to the front edge of the input signal and turning on the pull-down means in response to the front edge of the control signal;
• and
• a floating preventing means connected between the input node of the pull-down means and a second power voltage, for always connecting the second power voltage to the input node of the pull-down means to prevent the input node of the pull-down means from being floated.

An LCD comprising a display cell array circuit, a data driving circuit and a gate driving circuit formed on a transparent substrate, the display cell array circuit comprising multiple data lines and multiple gate lines, each of the display cell arrays connected to a corresponding pair of data line and gate line,

• wherein the data driving circuit comprises multiple data line blocks and a shift register,
• wherein each of the data line blocks comprises multiple driving transistors each of which drain and source are respectively connected between a data input terminal and the data line and gate is commonly connected to a block selection terminal,
• wherein the shift register comprises multiple stages connected one after another to each other, the multiple stages having a first stage in which a block selection start signal is coupled to an input terminal, for sequentially selecting the multiple data line blocks using an output signal of each stage, and the multiple stages consisting of odd stages for receiving a first clock signal;
• and even stages for receiving a second clock signal having a phase opposite to the first clock signal,
• wherein each stage comprises:
• an input terminal connected to an output terminal of a previous stage;
• an output terminal connected to a block selection terminal of a corresponding data line block;
• a control terminal connected to an output terminal of a next stage;
• a clock terminal into which a corresponding clock signal is input;
• a pull-up means connected between the clock terminal and the output terminal, for pulling-up the corresponding gate line during a duty period of the clock signal of when the pull-up means is turned on;
• a pull-down means connected between the output terminal and a first power voltage, for pulling-down the corresponding gate line using the first power voltage when the pull-down means is turned on;
• a pull-up driving means connected to an input node of the pull-up means, for turning on the pull-up means in response to a front edge of an input signal supplied to the input terminal and turning off the pull-up means in response to a front edge of a control signal supplied to the control terminal;
• and
• a pull-down driving means connected to an input node of the pull-down means, for turning off the pull-down means in response to the front edge of the input signal and turning on the pull-down means in response to the front edge of the control signal.

An LCD having an LCD module in which a liquid crystal is interposed between a lower transparent substrate and an upper transparent substrate, the LCD comprising:

• a display cell array circuit formed on the lower transparent substrate, comprising multiple data lines and multiple gate lines, each of the display cell arrays connected to a corresponding pair of data line and gate line,
• a gate driving circuit formed on the lower transparent substrate and comprising a first shift register comprising multiple stages connected one after another to each other, the multiple stages having a first stage in which a start signal is coupled to an input terminal, the first shift register sequentially selecting the multiple gate lines using an output signal of each stage;
• a data driving circuit formed on the lower transparent substrate and comprising multiple data line blocks and a second shift register, each of the data line blocks comprising multiple driving transistors each of which drain and source are connected between a data input terminal and the data line and gate is commonly connected to a block selection terminal, the second shift register comprising multiple stages connected one after another to each other, the multiple stages having a first stage in which a block selection start signal is coupled to an input terminal, for sequentially selecting the multiple data line blocks using an output signal of each stage;
• and
• a flexible PCB on which an integral control and data driving chip is mounted, for providing a control signal and a data signal to the input terminal of the gate and data driving circuits.

A shift register in which multiple stages are connected one after another to each other, the multiple stage having a first stage in which a start signal is inputted into an input terminal, the shift register sequentially outputting output signals of respective stages, the multiple stages including odd stages for receiving a first clock signal and even stages for receiving a second clock signal having a phase opposite to the first clock signal,

• each of the multiple stages comprising:
• a pull-up means for providing a corresponding one of the first and second clock signals to an output terminal;
• a pull-up driving means, connected to an input node of the pull-up means, for charging a capacitor in response to a front edge of an input signal to turn on the pull-up means and discharging the capacitor in response to a front edge of an output signal of a next stage to turn off the pull-up means;
• a pull-down means for providing a first power voltage to the output terminal;
• and
• pull-down driving means, connected to an input node of the pull-down means and the input node of the pull-up means, for turning off the pull-down means and turning on the pull-down means in response to the front edge of the output signal of the next stage.

A shift register in which multiple stages are connected one after another to each other, the multiple stage having a first stage in which a start signal is inputted into an input terminal, the shift register sequentially outputting output signals of respective stages, the multiple stages including odd stages for receiving a first clock signal and even stages for receiving a second clock signal having a phase opposite to the first clock signal,

• each of the multiple stages comprising:
• an NMOS pull-up transistor of which drain is connected to a corresponding clock signal, gate is connected to a first node and source is connected to an output terminal;
• an NMOS pull-down transistor of which drain is connected to the output terminal, gate is connected to a second node and source is connected to a first power voltage;
• a capacitor connected between the first node and the output terminal;
• a first transistor of which drain is connected to a second power voltage, gate is connected to an input signal and source is connected to the first node;
• a second transistor of which drain is connected to the first node, gate is connected to an output signal of a next stage and source is connected to the first power voltage;
• a third transistor of which drain is connected to the first node, gate is connected to the second node and source is connected to the first power voltage;
• a fourth transistor of which drain and gate are commonly connected to the second power voltage and source is connected to the second node;
• and
• a fifth transistor of which drain is connected to the second node, gate is connected to the first node and source is connected to the first power voltage.

A shift register including multiple stages connected in a cascade fashion, the multiple stages having a first stage in which a start signal is coupled to an input terminal, for sequentially outputting output signals of the respective stages, the multiple stages having odd stages for receiving a first clock signal and a second clock signal having a phase opposite to the first clock signal at a first clock terminal and a second clock terminal of the odd stages, and even stages for receiving the second clock signal and the first clock signal at a first clock termianl and a second clock terminal of the even stages,

• wherein each of the multiple stages comprises:
• an input terminal connected to an output terminal of a previous stage;
• an output terminal connected to a corresponding gate line;
• a first control terminal connected to a second control terminal of a stage after a next stage;
• a second control terminal;
• a clock terminal into which a corresponding clock signal is inputted;
• a pull-up means for providing a corresponding one out of the first and second clock signals to the output terminal;
• a pull-down means for providing a first power voltage to the output terminal;
• a pull-up driving means connected to an input node of the pull-up means, for turning on the pull-up means in response to a front edge of an input signal and turning off the pull-up means in response to a front edge of a control signal supplied to the control terminal;
• and
• a pull-down driving means connected to an input node of the pull-down means and an input node of the pull-up means, for turning off the pull-down means, and for turning on the pull-down means in response to a front edge of an output signal of the next stage.

An LCD comprising a display cell array circuit, a data driving circuit and a gate driving circuit formed on a transparent substrate, the display cell array circuit comprising multiple data lines and multiple gate lines, each of the display cell arrays connected to a corresponding pair of data line and gate line,

• the gate driving circuit comprising a shift register including multiple stages connected in a cascade fashion, the multiple stages having a first stage in which a start signal is coupled to an input terminal, the shift register for sequentially outputting output signals of the respective stages, the multiple stages having odd stages for receiving a first clock signal and a second clock signal having a phase opposite to the first clock signal at a first clock terminal and a second clock terminal of the odd stages, and even stages for receiving the second clock signal and the first clock signal at a first clock termianl and a second clock terminal of the even stages,
• wherein each of the multiple stage comprises:
• an input terminal connected to an output terminal of a previous stage;
• an output terminal connected to a corresponding gate line;
• a first control terminal connected to a second control terminal of a stage after a next stage;
• a second control terminal;
• a clock terminal into which a corresponding clock signal is inputted;
• a pull-up means connected between the clock terminal and the output terminal, for turning on the corresponding gate line during a duty period of the clock signal;
• a pull-down means connected between the output terminal and a first power voltage, for pulling-down the corresponding gate line when the pull-down means is turned on;
• a pull-up driving means connected to an input node of the pull-up means, for turning on the pull-up means in response to a front edge of an input signal supplied to the input terminal and turning off the pull-up means in response to a front edge of a control signal of the stage after the next stage supplied to the control terminal;
• and
• a pull-down driving means connected to an input node of the pull-down means and an input node of the pull-up means, for turning off the pull-down means and for turning on the pull-down means in response to a front edge of an output signal of the next stage.

A shift register including multiple stages connected in a cascade fashion, the multiple stages having a first stage in which a start signal is coupled to an input terminal, for sequentially outputting output signals of the respective stages, the multiple stages including odd stages for receiving a first clock signal and a second clock signal having a phase opposite to the first clock signal,

• wherein each of the multiple stages comprises:
• a pull-up means for providing a corresponding one out of the first and second clock signals;
• a pull-down means for providing a first power voltage to the output terminal;
• a pull-down driving means connected to an input node of the pull-down means, for turning off the pull-down means in response to a front edge of the input signal and turning on the pull-down means in response to a front edge of an output signal of a next stage;
• and
• a pull-up driving means provided with a capacitor of which a first end is connected to an input node of the pull-up means and a second end is connected to the output terminal, and a discharging means for forcibly discharging the capacitor depending on an external input control signal, the pull-up driving means turning on the pull-up means by charging the capacitor in response to the front edge of the input signal and turning off the pull-up means by forcibly discharging the capacitor in response to the front edge of the output signal of the next stage.

An LCD comprising a display cell array circuit, a data driving circuit and a gate driving circuit formed on a transparent substrate, the display cell array circuit comprising multiple data lines and multiple gate lines, each of the display cell arrays connected to a corresponding pair of data line and gate line,

• the gate driving circuit comprising a shift register including multiple stages connected in cascade fashion, the multiple stages having a first stage in which a start signal is coupled to an input terminal, the shift register for sequentially selecting the multiple gate lines depending on output signals of the respective stages, the multiple stages having odd stages for receiving a first clock signal, and even stages for receiving a second clock signal having a phase opposite to the first clock signal,
• wherein each of the multiple stages comprises:
• an input terminal connected to an output terminal of a previous stage;
• an output terminal connected to a corresponding gate line;
• a control terminal connected to a control terminal of a next stage;
• a clock terminal into which a corresponding clock signal is inputted;
• an external input control terminal for receiving an external input control signal;
• a pull-up means for providing a corresponding one out of the first and second clock signals to the output terminal;
• a pull-down means for providing a first power voltage to the output terminal;
• a pull-down driving means connected to an input node of the pull-down means, for turning off the pull-down means in response to a front edge of the input signal and turning on the pull-down means in response to a front edge of an output signal of a next stage;
• and
• a pull-up driving means provided with a capacitor of which one end is connected to an input node of the pull-up means and the other end is connected to the output terminal, and a discharging means for forcibly discharging the capacitor depending on the external input control signal applied to the external input control terminal, the pull-up driving means turning on the pull-up means by charging the capacitor in response to the front edge of the input signal and turning off the pull-up means by forcibly discharging the capacitor in response to the front edge of the output signal of the next stage.