Power efficient emitter-coupled logic circuit

A low power consumption emitter-coupled logic (ECL) circuit comprising:

• a current-mode logic (CML) circuit having an input to receive an input signal, a logic function having a level of series gated logic, first and second differential output signals responsive to the input signal and logic function, and is powered by a first power supply (Vcc) and a third power supply (Vee3) that is approximately equal to:
• Vcc−(0.4+((level of series gated logic)*(0.9 volts))).

A high bandwidth emitter-coupled logic (ECL) circuit with reduced power consumption, the ECL circuit comprising:

• a current-mode logic (CML) circuit including a logic function having a level of series gated logic, connected to a first power supply (Vcc) and to a third power supply (Vee3) having a voltage approximately equal to Vcc−(0.4+((the level of series gated logic)*(0.9 volts))), having an input to accept an input signal, an input to accept a differential signal approximately 180 degrees out of phase from the input signal, an output to supply a first signal in response to the input signal, and an output to supply a second signal, approximately 180 degrees out of phase from the first signal;
• and,
• an emitter-follower circuit connected to the first,power supply and to a second power supply (Vee2) approximately 1.5 volts less than the first power supply, having an input to accept the first signal, an input to accept the second signal, an output to supply a third signal responsive to the first signal, and an output to supply a fourth signal responsive to the second signal.