US 6,690,192 B1Granted

Current-compensated CMOS output buffer adjusting edge rate for process, temperature, and Vcc variations

AssigneePericom Semiconductor Corp.

InventorChoy Kwok Wing

Life of this patent

Estimating the term…

Loading patent…

Abstract

Edge rates for output driver transistors are increased for slower conditions such as caused by supply-voltage, temperature, and process variations. The edge rates are increased by increasing charging and discharging currents to the gates of the driver transistors. Process-sensing transistors have gates tied to power or ground. Current through the process-sensing transistors changes with supply-voltage, temperature, and process variations. The currents through process-sensing transistors are used to generate process-compensated voltages that bias current sources and sinks to adjust process-dependent currents. Process-independent or fixed current sources and sinks use process-independent reference voltages ultimately generated from reference currents that are not sensitive to process variations. The process-dependent-currents are subtracted from the fixed currents to produce the charging and discharging currents.

Claims20

Dependent claims

A process-compensated output buffer comprising:

a reference voltage generator, receiving a reference current having substantially no process dependency, for generating p-channel reference voltages and n-channel reference voltages having substantially little process dependency;
a PMOS process compensator, receiving the p-channel reference voltages from the reference voltage generator, for generating a first control voltage between a;
frost fixed current source that receives the p-channel reference voltages and a frost process-compensated current sink;
a first control transistor for adjusting discharge current from a p-driver gate in response to the first control voltage;
an NMOS process compensator for generating process-compensated voltages that have a substantial process dependency;
an NMOS edge-rate increaser, receiving the n-channel reference voltages from the reference voltage generator and the process-compensated voltages from the NMOS process compensator, for generating a second control voltage between a fixed current sink that receives the n-channel reference voltages and a process-compensated current source that receives the process-compensated voltages;
and
a second control transistor for adjusting charge current to an n-driver gate in response to the second control voltage,
whereby charge and discharge currents of driver gates are process-compensated.

6 more elements

A buffer having internal currents compensated for supply-voltage, temperature, and process variations comprising:

a pull-up driver transistor for driving pull-up current to an output in response to a first gate;
a pull-down driver transistor for sinking pull-down current from the output in response to a second gate;
a first control transistor for controlling current to the first gate in response to a first control voltage;
a second control transistor for controlling current to the second gate in response to a second control voltage;
a first fixed current source for producing a first fixed current that is relatively insensitive to supply-voltage, temperature, and process variations;
a first variable current sink for sinking a first variable current that is more sensitive to supply-voltage, temperature, and process variations than is the first fixed current;
a first mirror transistor, coupled to receive a first current difference, for generating the first control voltage in response to the first current difference, the first current difference being a difference between the first fixed current and the first variable current;
a second fixed current sink for sinking a second fixed current that is relatively insensitive to supply-voltage, temperature, and process variations;
a second variable current source for producing a second variable current that is more sensitive to supply-voltage, temperature, and process variations than is the second fixed current;
and
a second mirror transistor, coupled to supply a second current difference, for generating the second control voltage in response to the second current difference, the second current difference being a difference between the second variable current and the second fixed current,
whereby current differences between fixed and process-variable current sources control currents to gates of driver transistors.

9 more elements

A compensated output buffer comprising:

reference voltage generator means, receiving a reference current having substantially no process dependency, for generating p-channel reference voltages and n-channel reference voltages having substantially little process dependency;
PMOS process compensator means, receiving the p-channel reference voltages from the reference voltage generator means, for generating a first control voltage between a fixed current source that receives the p-channel reference voltages and a compensated current sink;
first control transistor means for adjusting discharge current from a p-driver gate in response to the first control voltage;
NMOS process compensator means for generating compensated voltages that have a substantial process dependency;
NMOS edge-rate adjust means, receiving the n-channel reference voltages from the reference voltage generator means and the compensated voltages from the NMOS process compensator means, for generating a second control voltage between a fixed current sink that receives the n-channel reference voltages and a compensated current source that receives the compensated voltages;
and
second control transistor means for adjusting charge current to an n-driver gate in response to the second control voltage,
whereby charge and discharge currents of driver gates are compensated.

5 more elements

Dependencies are inferred from the claim text.