Method of fabricating a three-dimensional array of active media
AssigneeIntel Corporation
InventorJeff J. Peterson
Life of this patent
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Abstract
An apparatus comprising control circuitry formed on a substrate, and a plurality of active media coupled to the control circuitry and formed in a plurality of planes over the substrate. A method comprising forming a pair of junction regions on a substrate separated by a channel length; and forming a channel material overlying and coupled to the pair of junction regions having a dimension at least equal to the channel length. An apparatus comprising a contact formed in a first plane over a device structure; and a device coupled to the contact and formed in a second plane a greater distance from the substrate than the first plane.
Claims29
An apparatus comprising:
- control circuitry formed on a substrate, wherein the control circuitry comprises a conductor;
- and
- a plurality of active media coupled to the conductor and formed in a plurality of planes over the substrate, wherein adjacent ones of the plurality of active media are separated by a distance less than a minimum feature size of respective ones of the plurality of active media.
An apparatus comprising:
- a plurality of first address lines and a plurality of second address lines on a substrate;
- a plurality of active media formed in a plurality of planes over the substrate, adjacent ones of the plurality of active media separated by a distance less than a minimum feature size and each of the plurality of active media coupled to respective ones of a plurality of first address lines and a plurality of second address lines;
- and
- addressing circuitry coupled to the plurality of first address lines and the plurality of second address lines.
An apparatus comprising:
- a dedicated memory chip comprising a plurality of first address lines and a plurality of second address lines on a substrate;
- a plurality of units of programmable material formed in a plurality of planes over the substrate, adjacent ones of the plurality of active media separated by a distance less than a minimum feature size and each of the plurality units of programmable material coupled to respective ones of a plurality of first address lines and a plurality of second address lines;
- and
- addressing circuitry coupled to the plurality of first address lines and the plurality of second address lines.
A method comprising:
- forming a conductor on a first level;
- forming a plurality of units of active media on a second level;
- forming adjacent units of active media in different planes over a third level, the adjacent units of active media separated by a distance less than a minimum feature size;
- coupling the plurality of units on the second level to the conductor;
- and
- coupling the adjacent units of active media over the third level to the conductor.
A method comprising:
- forming a plurality of active layers over a device layer of a substrate in a stacked configuration;
- in each active layer forming a pair of junction regions in a single plane the active layer separated by a channel;
- and
- in each active layer forming a gate electrode on the channel.
A method comprising:
- forming a pair of junction regions on a substrate separated by a channel length;
- and
- forming a channel material overlying and coupled to the pair of junction regions having a dimension at least equal to the channel length.
An apparatus comprising:
- a contact formed in a first plane over a device structure;
- and
- a device coupled to the contact and formed in a second plane a greater distance from the substrate than the first plane.
Dependencies are inferred from the claim text.