High-level synthesis method, high-level synthesis apparatus, method for producing logic circuit using the high-level synthesis method for logic circuit design, and recording medium

#1. Field of the Invention

#The present invention relates to a high-level synthesis method and apparatus for automatically generating a logic circuit for a semiconductor integrated circuit (LSI) represented by a behavioral description in which processing behaviors are described, and also relates to a method for producing a logic circuit using the high-level synthesis method for logic circuit design, and a recording medium. More particularly, the present invention relates to a high-level synthesis method and apparatus for automatically generating an interface circuit used to interface with a bus having a predetermined protocol so as to perform data transfer with an external circuit, such as a general-purpose CPU, based on a behavioral description described in a language having a high level of abstractness, such as the C language, with the method and apparatus being used to synthesize a hard-wired circuit, and also relates to a method for producing a logic circuit using the high-level synthesis method for logic circuit design, and a recording medium.

#2. Description of the Related Art

#FIG. 1 is a block diagram showing a configuration of a high-level synthesis apparatus according to an embodiment of the present invention.

#FIG. 2 is a diagram showing an example of a behavioral description stored ina behavioral description storing section shown in FIG. 1.

#FIG. 3 is a diagram showing a control data flow graph generated by a CDFG generating section shown in FIG. 1.

#Hereinafter, the present invention will be described by way of illustrative examples with reference to the accompanying drawings.

#FIG. 1 is a block diagram showing a configuration of a high-level synthesis apparatus according to an embodiment of the present invention. In FIG. 1, a high-level synthesis apparatus 1 includes a behavioral description storing section 2, a behavioral description analyzing section 3, a bus connection resource extracting section 4, a bus connection resource database 5, a CDFG generating section 6, a scheduling section 7, an allocation section 8, a data path generating section 9, a controller generating section 10, a bus protocol library 11, a bus interface generating section 12, an RT level circuit description generating section 13, and an RT level circuit description storing section 14. A bus interface circuit automatically generated by the bus interface generating section 12 is attached to an operator, a register, a data path, a controller circuit, and the like, which are generated based on a behavioral description. As a result, an entire RT level circuit is synthesized.

#The behavioral description storing section 2 is used to store a behavioral description in which processing behaviors are described. For explanation purposes only, a behavioral description is written in “Bach-C”. “Bach-C” is a member of a language family for supporting LSI design based on a description of a system algorithm. Bach-C is created based on the C language, and has additional features: data bit-width specification; a syntax for explicit parallelism; and data communication instructions for parallelism. The further details of Bach-C are described in “Bach: Environment for LSI Design with C Language”, The 11th Workshop on Circuits and Systems in Karuizawa, Apr. 20-21, 1998, and “Hardware Complier Bach”, TECHNICAL REPORT OF IEICE CPSY97-87 (1997-10).