Method and apparatus for pre-computing routes for multiple wiring models
AssigneeCadence Design Systems, Inc.
InventorsSteven Teig, Joseph L. Ganley
Life of this patent
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AssigneeCadence Design Systems, Inc.
InventorsSteven Teig, Joseph L. Ganley
Estimating the term…
Some embodiments provide a method of pre-computing routes for nets in a region of an integrated circuit (“IC”) layout. The method initially defines a set of partitioning lines for partitioning the region into a plurality of sub-regions during a routing operation. For a particular set of potential sub-regions, the method then identifies a first set of routes based on a first wiring model and a second set of routes based on a second wiring model. Each identified set of routes traverses the particular set of potential sub-regions. The method then stores the identified routes.
For a router that uses a set of partitioning lines for partitioning a region of an integrated circuit layout into a plurality of sub-regions, a method of pre-computing routes, the method comprising:
For an electronic design automation (“EDA”) application, a method of pre-computing routes for nets, the method comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
Circuit design at the physical level: routing
Routing: detailed
Arrangements for mechanically moving the whole head: sled-type positioners
Term ended 19 Jan 2022 (estimated)
The invention provides method and apparatus for pre-computing routes for multiple wiring models.
An integrated circuit (“IC”) is a device that includes many electronic components (e.g., transistors, resistors, diodes, etc.). These components are often interconnected to form multiple circuit components (e.g., gates, cells, memory units, arithmetic units, controllers, decoders, etc.) on the IC. The electronic and circuit components of IC's are jointly referred to below as “components.”
An IC also includes multiple layers of wiring (“wiring layers”) that interconnect its electronic and circuit components. For instance, many IC's are currently fabricated with metal or polysilicon wiring layers (collectively referred to below as “metal layers”) that interconnect its electronic and circuit components. One common fabrication model uses five metal layers. In theory, the wiring on the metal layers can be all-angle wiring (i.e., the wiring can be in any arbitrary direction). Such all-angle wiring is commonly referred to as Euclidean wiring. In practice, however, each metal layer typically has a preferred wiring direction, and the preferred direction alternates between successive metal layers. Many IC's use the Manhattan wiring model, which specifies alternating layers of preferred-direction horizontal and vertical wiring. In this wiring model, the majority of the wires can only make 90° turns. However, occasional diagonal jogs are sometimes allowed on the preferred horizontal and vertical layers.
The novel features of the invention are set forth in the appended claims. However, for purpose of explanation, several embodiments of the invention are set forth in the following figures.
FIG. 1 illustrates an example of an IC layout.
FIG. 2 illustrates an IC layout that utilizes horizontal, vertical, and 45° diagonal interconnect lines.
The invention is directed towards routing method and apparatus that utilize diagonal routes. In the following description, numerous details are set forth for purpose of explanation. However, one of ordinary skill in the art will realize that the invention may be practiced without the use of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order not to obscure the description of the invention with unnecessary detail.
Several embodiments of the invention's routing method and apparatus are described below. However, before discussing these embodiments, several diagonal wiring architectures that can be used with these embodiments are described in Section I.
I. DIAGONAL WIRING ARCHITECTURE