Method for layout design and timing adjustment of logically designed integrated circuit
AssigneeFujitsu Limited
InventorHiroshi Sato
Life of this patent
Estimating the term…
Abstract
Reading out data of a logically designed circuit (S1); replacing flip-flops in the circuit with respective scan flip-flops with LUL, and cascading the scan flip-flops with LUL with respect to scan-in and scan-out to form a scan circuit (S2); laying out the changed logically designed circuit (S3); replacing the scan flip-flops with LUL with ordinary scan flip-flops (S4); performing a static timing analysis (S6); and if timing error occurs, replacing a corresponding ordinary scan flip-flop with a scan flip-flop with LUL (S7).
Claims12
A method for layout design and timing adjustment of a logically designed integrated circuit comprising a first logic circuit, said first logic circuit comprising a plurality of flip-flops, each having a master latch circuit and a slave latch circuit, said method comprising:
- preparing cell data of first and second scan flip-flops, said second scan flip-flop comprising said master latch circuit, said slave latch circuit cascaded to said master latch circuit, and a latch circuit connected to said slave latch circuit, wherein said latch circuit operates in a reverse state of said slave latch circuit of said second scan flip-flop with respect to holding and capturing;
- producing a second logic circuit from said first logic circuit by replacing said plurality of flip-flops with respective said second scan flip-flops, and by connecting said plurality of second scan flip-flops in cascade to each other to construct a first scan circuit;
- designing a layout of said second logic circuit;
- obtaining a third logic circuit from said second logic circuit by replacing said second scan flip-flops with respective said first scan flip-flops to form a second scan circuit;
- and
- performing a static timing analysis on said third logic circuit to adjust timing.
An apparatus for layout design and timing adjustment of a logically designed first integrated circuit comprising a first logic circuit, said first logic circuit comprising a plurality of flip-flops, each having a master latch circuit and a slave latch circuit, said apparatus comprising:
- a storage device storing data of said first logic circuit, cell data of first and second scan flip-flops, said second scan flip-flop comprising said master latch circuit, said slave latch circuit cascaded to said master latch circuit, and a latch circuit connected to said slave latch circuit, and a computer program, wherein said latch circuit operates in a reverse state of said slave latch circuit of said second scan flip-flop with respect to holding and capturing;
- and
- a computer executing said computer program;
- wherein said computer program causes said computer to perform:
- inputting said stored data;
- producing a second logic circuit from said first logic circuit by replacing said plurality of flip-flops with respective said second scan flip-flops, and by connecting said plurality of scan second flip-flops in cascade to each other to construct a first scan circuit;
- designing a layout of said second logic circuit;
- obtaining a third logic circuit from said second logic circuit by replacing said second scan flip-flops with respective said first scan flip-flops to form a second scan circuit;
- and
- performing a static timing analysis on said third logic circuit to adjust timing.
A computer program product, comprising:
- a computer readable storage medium having a computer program stored thereon for causing a computer to perform layout design and timing adjustment of a logically designed first integrated circuit comprising a first logic circuit, said first logic circuit comprising a plurality of flip-flops, each having a master latch circuit and a slave latch circuit, wherein said computer program causes said computer to perform:
- inputting data of said first logic circuit and cell data of first and second scan flip-flops, said second scan flip-flop comprising said master latch circuit, said slave latch circuit cascaded to said master latch circuit, and a latch circuit connected to said slave latch circuit, wherein said latch circuit operates in a reverse state of said slave latch circuit of said second scan flip-flop with respect to holding and capturing;
- producing a second logic circuit from said first logic circuit by replacing said plurality of flip-flops with respective said second scan flip-flops, and by connecting said plurality of scan second flip-flops in cascade to each other to construct a first scan circuit;
- designing a layout of said second logic circuit;
- obtaining a third logic circuit from said second logic circuit by replacing said second scan flip-flops with respective said first scan flip-flops to form a second scan circuit;
- performing a static timing analysis on said third logic circuit to adjust timing;
- and
- outputting a result of the timing adjustment.
A computer readable storage medium having a computer program stored thereon for causing a computer to perform layout design and timing adjustment of a logically designed first integrated circuit comprising a first logic circuit, said first logic circuit comprising a plurality of flip-flops, each having a master latch circuit and a slave latch circuit, wherein said computer program causes said computer to perform a process of:
- inputting data of said first logic circuit and cell data of first and second scan flip-flops, said second scan flip-flop comprising said master latch circuit, said slave latch circuit cascaded to said master latch circuit, and a latch circuit connected to said slave latch circuit, wherein said latch circuit operates in a reverse state of said slave latch circuit of said second scan flip-flop with respect to holding and capturing;
- producing a second logic circuit from said first logic circuit by replacing said plurality of flip-flops with respective said second scan flip-flops, and by connecting said plurality of scan second flip-flops in cascade to each other to construct a first scan circuit;
- designing a layout of said second logic circuit;
- obtaining a third logic circuit from said second logic circuit by replacing said second scan flip-flops with respective said first scan flip-flops to form a second scan circuit;
- performing a static timing analysis on said third logic circuit to adjust timing;
- and
- outputting a result of the timing adjustment.
Dependencies are inferred from the claim text.