Method and apparatus for hierarchical clock tree analysis
AssigneeAgilent Technologies, Inc.
InventorsStacey Secatch, James Hansen, Brian Mueller
Life of this patent
Estimating the term…
Abstract
A method for accurately analyzing the timing of a clock network on a piecemeal basis in an integrated circuit clock tree is presented. In accordance with the invention, the time delay of each individual subcircuit between an identified clock network node and an identified receiving endpoint may be individually determined. Tags are associated with the connection points of a child block and its parent block. A connection tool uses the tags to match up the connection points of the parent block to the respective connection points in the child block to allow a simulation tool to include the clock signal timing data of the child block in simulating the clock performance of the parent block.
Claims16
A method for analyzing clock skew in a hierarchical clock tree comprising one or more parent blocks each having one or more child blocks, said method comprising:
- obtaining one or more child block tags associated with respective child block nodes in said at least one child block;
- extracting one or more child block network subcircuits, each said child subcircuit comprising a child subcircuit input node and one or more child subcircuit endpoint nodes;
- for each said one or more child block network subcircuits, determining a time delay between said child subcircuit input node and each of said one or more child subcircuit endpoint nodes;
- obtaining one or more parent tags associated with respective parent block nodes in said at least one parent block;
- extracting one or more parent block network subcircuits, each said parent subcircuit comprising a parent subcircuit input node and one or more parent subcircuit endpoint nodes;
- for each said one or more parent block network subcircuits, determining a time delay between said parent subcircuit input node and each of said one or more parent subcircuit endpoint nodes;
- obtaining a map of said parent block tags to respective ones of said child block tags;
- connecting said respective parent block nodes associated with said one or more parent tags to said respective child block nodes associated with said one or more child tags mapped to said respective one or more parent tags;
- for each of said parent block subcircuits, determining said accumulated time delay between said parent subcircuit input node and each of said one or more child subcircuit endpoint nodes of child subcircuits connected to said parent subcircuit, taking into account said associated child subcircuit time delay and said respective parent subcircuit time delay associated with said parent block.
A system for analyzing clock skew in a hierarchical clock tree comprising one or more parent blocks each having one or more child blocks, said system comprising:
- an analysis tool which receives a child block network routing list of a child block, one or more child block tags associated with respective child block nodes in said child block, a parent block network routing list of a parent block, one or more parent tags associated with respective parent block nodes in said parent block, and a map of parent tags to child tags, which generates a child block netlist, one or more child block network subcircuits each comprising a child subcircuit input node and one or more child subcircuit endpoint nodes, a parent block netlist, and one or more parent block network subcircuits each comprising a parent subcircuit input node and one or more parent subcircuit endpoint nodes;
- and
- a simulation tool which receives said child block netlist and said one or more child block network subcircuits, and simulates said one or more child block network subcircuits to generate a time delay between said child subcircuit input node and each of said one or more child subcircuit endpoint nodes for each said one or more child block network subcircuits;
- and which receives said parent block netlist and said one or more parent block network subcircuits and simulates said one or more parent block network subcircuits to generate a time delay between said parent subcircuit input node and each of said one or more parent subcircuit endpoint nodes for each said one or more parent block network subcircuits;
- and which determines, for each of said parent block subcircuits, an accumulated time delay between said parent subcircuit input node and each of said one or more child subcircuit endpoint nodes of child subcircuits having nodes mapped to nodes of said parent subcircuit, taking into account said associated child subcircuit time delay and said respective parent subcircuit time delay associated with said parent block.
Dependencies are inferred from the claim text.