Testing for shorts between interconnect lines in a partially defective programmable logic device

A method of detecting shorts affecting nets of a specified design implemented in a partially defective programmable logic device (PLD) comprising interconnect lines and programmable interconnect points (PIPs) between the interconnect lines, the method comprising:

• identifying the nets used in the specified design;
• identifying potentially conflicting pairs of the nets that can be shorted together by an inadvertent enablement of a single PIP;
• dividing the nets into a plurality of groups, wherein no two of the nets in a single group form a potentially conflicting pair of the nets;
• applying a stimulus pattern to each net, wherein a first stimulus pattern is applied to each net in a first group, and a second stimulus pattern different from the first stimulus pattern is applied to each net in a second group;
• detecting value patterns on each of the nets while applying the stimulus patterns;
• and
• comparing the detected value patterns to the applied stimulus patterns for each net.

A method of detecting shorts affecting nets of a specified design implemented in a partially defective programmable logic device (PLD) comprising interconnect lines and programmable interconnect points (PIPs) between the interconnect lines, the method comprising:

• identifying the nets in the specified design;
• identifying potentially conflicting pairs of the nets that can be shorted together by an inadvertent enablement of a single PIP;
• dividing the nets into a plurality of groups, wherein no two nets in a single group form a potentially conflicting pair of nets that can be shorted together by an inadvertent enablement of a single PIP, a first group comprising a first net and a second group comprising a second net;
• and
• testing for a short between the first and second nets.

A computer-readable medium including stored instructions for testing for shorts between nets of a specified design implemented in a partially defective programmable logic device (PLD) comprising interconnect lines and programmable interconnect points (PIPs) between the interconnect lines, the computer-readable medium comprising:

• first computer instructions for applying a first stimulus pattern to a first net in the specified design;
• second computer instructions for applying a second stimulus pattern to a second net while applying the first stimulus pattern, the second stimulus pattern not being the same as the first stimulus pattern, the first and second nets being nets that can be shorted together by an inadvertent enablement of a single PIP;
• third computer instructions for detecting a value pattern on the first net while applying the first and second stimulus patterns;
• and
• fourth computer instructions for comparing the detected value pattern to the applied first stimulus pattern.

A computer-readable medium including stored instructions for testing for shorts between nets of a specified design implemented in a partially defective programmable logic device (PLD) comprising interconnect lines and programmable interconnect points (PIPs) between the interconnect lines, the computer-readable medium comprising:

• first computer instructions for applying a first value to each net in a group of nets of the specified design, wherein no two nets in the group can be shorted together by an inadvertent enablement of a single PIP;
• second computer instructions for applying a second value different from the first value to one or more interconnect lines not in the group;
• and
• third computer instructions for testing the nets in the group for the first value.