Methods and apparatuses for non-equivalence checking of circuits with subspace
AssigneeSynplicity, Inc.
InventorsKenneth S. McElvain, Sanjeev Mahajan
Life of this patent
Estimating the term…
Abstract
Methods and systems for designing integrated circuits. In one exemplary method, matched registers between the two netlists are determined. The matched registers become cut off points to generate primary inputs and outputs. When there are one or more unmatched registers between the first netlist and the second netlist, the unmatched registers are pushed to the primary inputs or outputs using retiming. At the primary inputs, a subspace generator is used to generate subspaces. The subspaces are used to identify non-equivalences between the first and second netlists. Other features and embodiments are also described.
Claims33
A method, comprising:
- comparing a reference netlist with a test netlist to determine cut off points from a set of matched registers in the reference netlist and in the test netlist, the cut off points dividing the reference netlist and the test netlist into multiple reference circuits and test circuits respectively;
- forming primary inputs and outputs at the cut off points;
- forming a plurality of subspaces of inputs using the primary inputs for the reference circuits and the test circuits;
- and
- identifying non-equivalences between the reference netlist and the test netlist using the plurality of subspaces.
A computer readable medium containing executable computer program instructions which when executed by a processing system cause said processing system to perform a method comprising:
- comparing a reference netlist with a test netlist to determine cut off points from a set of matched registers in the reference netlist and in the test netlist, the cut off points dividing the reference netlist and the test netlist into multiple reference circuits and test, circuits respectively;
- forming primary inputs and outputs at the cut off points;
- forming a plurality of subspaces of inputs using the primary inputs for the reference circuits and the test circuits;
- and
- identifying non-equivalences between the reference netlist and the test netlist using the plurality of subspaces.
A system, comprising:
- a memory to store a reference netlist and a test netlist;
- and
- a processor coupled with the memory, the processor configured to:
- compare the reference netlist with the test netlist to determine cut off points from a set of matched registers in the reference netlist and in the test netlist, the cut off points dividing the reference netlist and the test netlist into multiple reference circuits and test circuits respectively;
- form primary inputs and outputs at the cut off points;
- form a plurality of subspaces of inputs using the primary inputs for the reference circuits and the test circuits;
- and
- identify non-equivalences between the reference netlist and the test netlist using the plurality of subspaces.
A system comprising:
- means for identifying matched registers between a first netlist with a second netlist to form primary inputs;
- means for generating a plurality of subspaces using the primary inputs;
- and
- means for identifying non-equivalences between the first netlist and the second netlist using the plurality of subspaces.
Dependencies are inferred from the claim text.