On-chip service processor for test and debug of integrated circuits

An integrated circuit comprising:

• an interface for coupling to an external diagnostic processor;
• an analysis engine implemented in the form of an on-chip logic analyzer having channels adapted to capture sequential snapshots of system-operation signals of said integrated circuit,
• a plurality of probe lines coupled to said analysis engine for carrying said system operation signals from a set of selectively enabled probe points of said integrated circuit, wherein the selectively enabled probe points are selected from a set of pre-existing probe points coupled to the channels of said analysis engine and turned on by enabling circuits, wherein said probe lines are capable of moving said sets of sequential system operation signals at one or more system operation clock rates;
• and
• a memory coupled to said analysis engine and to said interface, said sets of sequential system operation signals being stored in said memory at one or more clock signal rates internal to said integrated circuit and retrieved from said memory through said interface to said external processor at one or more clock signal rates external to said integrated circuit so that said external diagnostics processor can process said captured system operation signals.

A method of operating an integrated circuit having logic blocks, a control unit, an analysis engine implemented in the form of an on-chip logic analyzer, a memory and a plurality of probe lines of said logic blocks, said method comprising:

• operating said logic blocks to perform normal system operations at one or more system clock signal rates internal to said integrated circuit to produce sets of system operation signals;
• selectively enabling a subset of said probe lines responsive to said control unit, wherein the enabling of said probe lines is performed by turning on enabling circuits associated with said analysis engine, to capture and carry sets of system operation signals of said logic blocks at said system clock signal rates internal to said integrated circuit;
• moving, via channels of said analysis engine coupled to said probe lines, captured sets of system operation signals from said logic blocks along said probe lines at said system clock signal rates internal to said integrated circuit;
• storing said captured sets of system operation signals in said memory at said system clock signal rates internal to said integrated circuit;
• and
• processing said sets of stored system operation signals to perform test and debug operations of said logic blocks of said integrated circuit.