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US 6,687,864 B1Granted
Macro-cell flip-flop with scan-in input
AssigneeCypress Semiconductor Corporation
InventorsAnup Nayak, Ramin Ighani, Sanjeev Kumar Maheshwari
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Abstract
A programmable logic device comprising a macro-cell flip-flop configured to store (i) a first input when the programmable logic device is in a normal mode and (ii) a second input when the programmable logic device is in a test mode.
Claims23
A programmable logic device having a macro-cell comprising:
- a multiplexer circuit configured to present (i) a first input as an output in response to a first state of a first control signal and (ii) a second as said output in response a second state of said first control signal;
- and
- a flip-flop circuit configured to store said output in response to a clock signal.
A programmable logic device comprising:
- a first macro-cell flip-flop configured to generate a first output signal in response to a first input signal, a second input signal, a first control signal and a first clock signal, wherein said first macro-cell flip-flop stores (i) a state of said first input signal in response to said first clock signal and a first state of said first control signal and (ii) a state of said second input signal in response to said first clock signal and a second state of said first control signal;
- and
- a second macro-cell flip-flop configured to generate a second output signal in response to (i) said first output signal (ii) a third input signal, said first control signal and a second clock signal, wherein said second macro-cell flip-flop stores (i) a state of said first output signal in response to said second clock signal and said first state of said first control signal and (ii) a state of said third input signal in response to said second clock signal and said second state of said first control signal.
A method for forming a scan chain containing a number of macro-cell flip-flops of a programmable logic device comprising the steps of:
- (A) generating a first control signal having a first state during a test mode and a second state during a normal mode of said programmable logic device;
- (B) during said test mode, (i) deselecting a first input to each of said number of macro-cell flip-flops and (ii) selecting a second input to each of said number of macro-cell flip-flops in response to said first state of said first control signal, wherein an output of a first of said number of macro-cell flip-flops is coupled to said second input of a second of said number of macro-cell flip-flops;
- and
- (C) during said normal mode, (i) selecting said first input to each of said number of macro-cell flip-flops and (ii) deselecting said second input to each of said number of macro-cell flip-flops in response to said second state of said first control signal, wherein said first input of said number of macro-cell flip-flops is connected to programmable logic of said programmable logic device.
1 more element
Dependencies are inferred from the claim text.