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US 6,687,857 B1Granted
Microcomputer which can execute a monitor program supplied from a debugging tool
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsShunichi Iwata, Takashi Nasu, Fumitaka Fukuzawa
Life of this patent
Estimating the term…
Abstract
A microcomputer comprises a serial interface for receiving a debugging program applied thereto from a debugging tool, a register for holding an instruction code included with the debugging program, which is applied to the microcomputer via the serial interface, and a central processing unit or CPU for executing the instruction code held by the first register to debug the microcomputer. The microcomputer can further comprise a buffer for holding one or more instruction codes supplied thereto from the register. The CPU can execute each of the plurality of instruction codes held by the buffer. Preferably, the serial interface is a JTAT (Joint Test Action Group) interface.
Claims18
A microcomputer comprising:
- a serial interface for receiving a debugging program applied thereto from a debugging tool;
- a first register for holding an instruction code included with the debugging program, which is applied to said microcomputer via said serial interface;
- a central processing unit or CPU for executing the instruction code held by said first register;
- and
- a buffer for holding one or more instruction codes supplied thereto from said first register, wherein said CPU executes the instruction code held by said buffer.
2 more elements
A microcomputer comprising:
- a serial interface for receiving a debugging program applied thereto from a debugging tool;
- a first register for holding an instruction code included with the debugging program, which is applied to said microcomputer via said serial interface;
- a central processing unit or CPU for executing the instruction code held by said first register;
- and
- valid control means for generating a valid signal indicating whether the instruction code held by said first register is valid or invalid, and a second register for holding the value of the valid signal generated by said valid control means, for enabling said debugging tool to read the value of the valid signal by way of said serial interface.
2 more elements
A microcomputer comprising:
- a serial interface for receiving a debugging program applied thereto from a debugging tool;
- a first register for holding an instruction code included with the debugging program, which is applied to said microcomputer via said serial interface;
- a central processing unit or CPU for executing the instruction code held by said first register;
- and
- valid control means for generating a valid signal indicating whether the instruction code held by said first register is valid or invalid, and internal bus interface means for furnishing a negated access completion signal to said CPU when the valid signal generated by said valid control means indicates that the instruction code held by said first register is invalid, and for furnishing an asserted access completion signal to said CPU when the valid signal generated by said valid control means indicates that the instruction code held by said first register is valid.
2 more elements
A microcomputer comprising:
- a serial interface for receiving a debugging program applied thereto from a debugging tool;
- a first register for holding an instruction code included with the debugging program, which is applied to said microcomputer via said serial interface;
- a central processing unit or CPU for executing the instruction code held by said first register;
- and
- valid control means for generating a valid signal indicating whether the instruction code held by said first register is valid or invalid, and output control means, responsive to an instruction-fetching request from said CPU, for furnishing a branch instruction to prevent a program counter's current value from incrementing to said CPU when the valid signal generated by said valid control means indicates that the instruction code held by said first register is invalid.
2 more elements
A microcomputer comprising:
- a serial interface for receiving a debugging program applied thereto from a debugging tool;
- a first register for holding an instruction code included with the debugging program, which is applied to said microcomputer via said serial interface;
- a central processing unit or CPU for executing the instruction code held by said first register;
- and
- a second register for holding parameters applied thereto only by way of said serial interface, wherein said CPU can read the parameters held by said second register.
2 more elements
A microcomputer comprising:
- a serial interface for receiving a debugging program applied thereto from a debugging tool;
- a first register for holding an instruction code included with the debugging program, which is applied to said microcomputer via said serial interface;
- a central processing unit or CPU for executing the instruction code held by said first register;
- a second register for holding data applied thereto by way of said serial interface, wherein said CPU can read the data held by said second register;
- and
- valid control means for generating a valid signal indicating whether data held by said second register is valid or invalid, and a third register for holding the value of the valid signal generated by said valid control means and for enabling said debugging tool to read the value of the valid signal by way of said serial interface.
3 more elements
Dependencies are inferred from the claim text.