Method for correcting clock duty cycle skew by adjusting a delayed clock signal according to measured differences in time intervals between phases of original clock signal
AssigneeIntel Corporation
InventorBinglong Zhang
Life of this patent
Estimating the term…
Abstract
A device and method to detect and correct clock duty cycle skew detected in high performance microprocessor having a very high frequency clock. The device relies on a delay chain circuit to delay the clock signal and determine the presence of clock duty cycle skew. The device uses simple latches, flops and phase-detectors to compare and identify the nature of the clock duty cycle skew. Simple logic is then employed to measure and determine the amount and direction of de-skew to apply to the clock signal. After the de-skew operation, the clock duty cycle cycles used to control the execution of the microprocessor are of uniform time duration.
Claims22
A method of correcting clock duty cycle skew, comprising:
- generating a clock signal having clock cycles;
- delaying the clock signal by a clock cycle to generate a delayed clock signal;
- measuring the time interval between a phase 1 clock cycle and a phase 2 clock cycle in the clock signal and storing it as a first time period;
- measuring the time interval between the phase 2 clock cycle and a second phase 1 clock cycle in the clock signal and storing it as a second time period;
- determining when a delayed phase 2 clock cycle of the delayed clock cycle is high;
- subtracting the first time interval from the second time interval to yield a third time interval;
- and
- adjusting the start of the delayed phase 2 clock cycle by half of the third time interval so that the intervals between delayed clock cycles in delayed clock signal are of equal duration.
A device to correct clock duty cycle skew, comprising:
- a delay chain circuit to delay a clock signal and generate a delayed clock signal;
- a phase detector connected to the delay chain circuit to receive and compare the clock signal and delayed clock signal, wherein the phase detector will output a value of one or high when a leading edge of a clock cycle from the clock signal and a leading edge of a delayed clock cycle of the delayed clock signal are both high or equal to 1;
- a first latch connected to the clock signal and the phase detector to receive the clock signal and the output from the phase detector and generate a value of 1 or high;
- an inverter connected to the clock signal to clip of the value of the clock signal;
- a second latch connected to the inverter and the phase detector to receive the clock signal and the output from the phase detector and generate a value of 1 or high;
- and
- a skew logic unit connected to the first latch and the second latch to identify the presence of skew in the clock signal and adjust the delayed clock signal to compensate for the skew.
A computer program, comprising:
- monitoring a clock signal having clock cycles;
- delaying the clock signal by a clock cycle to generate a delayed clock signal;
- measuring the time interval between a phase 1 clock cycle and a phase 2 clock cycle in the clock signal and storing it as a first time period;
- measuring the time interval between the phase 2 clock cycle and a second phase 1 clock cycle in the clock signal and storing it as a second time period;
- determining when a delayed phase 2 clock cycle of the delayed clock cycle is high;
- subtracting the first time interval from the second time interval to yield a third time interval;
- and
- adjusting the start of the delayed phase 2 clock cycle by half of the third time interval so that the intervals between delayed clock cycles in delayed clock signal are of equal duration.
Dependencies are inferred from the claim text.