Back to results
US 6,687,843 B2Granted
Rambus DRAM with clock control circuitry that reduces power consumption
AssigneeHyundai Electronics Industries Co., Ltd.
InventorJong Tae Kwak
Life of this patent
Estimating the term…
Abstract
The present invention discloses a Rambus DRAM which can reduce power consumption by restricting generation of an unnecessary clock by improving command decryption when a command is applied with a COLC packet or COLX packet, so that the other packet cannot influence on another device.
Claims21
A Rambus DRAM comprising:
- an input signal detecting means including a first internal clock generating unit for generating a first internal clock signal according to a first comparing signal comparing an address value of a selected Rambus DRAM with an applied device address value of a COLC packet, and command code values in the COLC packet, when a command is applied with an SCP command packet on a Rambus DRAM module;
- a second internal clock generating unit for generating a second internal clock signal according to a second comparing signal comparing the address value of the selected Rambus DRAM with an applied device address value of a COLX packet, and command code values in the COLX packet;
- and a signal combining unit for generating an enable signal according to the first and second internal clock signals;
- a signal generating means for generating a clock enable signal for controlling an internal data to be externally output;
- an output signal maintaining means for generating to the signal generating means a control signal for maintaining the clock enable signal from the signal generating means in a read or current control command;
- and
- an output signal control means for receiving the enable signal from the input signal detecting means, generating a signal delayed longer than the enable signal by one cycle, and controlling the signal generating means to generate a clock enable signal delayed by one cycle by using the delayed signal in the read or current command, and to restrict generation of the clock enable signal when the command is not the read or current control command.
4 more elements
A Rambus DRAM comprising:
- an input signal detecting circuit arrangement including a first internal clock generator for generating a first internal clock signal according to a first comparing signal comparing an address value of a selected Rambus DRAM with an applied device address value of a COLC packet, and command code values in the COLC packet, when a command is applied with an SCP command packet on a Rambus DRAM module;
- a second internal clock generator for generating a second internal clock signal according to a second comparing signal comparing the address value of the selected Rambus DRAM with an applied device address value of a COLX packet, and command code values in the COLX packet;
- and a signal combiner constructed and arranged to generate an enable signal according to the first and second internal clock signals;
- a signal generator constructed and arranged to generate a clock enable signal for controlling an internal data to be externally output;
- an output signal maintaining circuit arrangement constructed and arranged to generate to the signal generator a control signal useful for maintaining the clock enable signal from the signal generator in a read or current control command;
- and
- an output signal control circuit arrangement constructed and arranged to receiving the enable signal from the input signal detecting circuit arrangement, generate a signal delayed longer than the enable signal by one cycle, and controlling the signal generator to generate a clock enable signal delayed by one cycle by using the delayed signal in the read or current command, and to restrict generation of the clock enable signal when the command is not the read or current control command.
4 more elements
Dependencies are inferred from the claim text.