Low-power processor hint, such as from a PAUSE instruction
AssigneeIntel Corporation
InventorsDoron Orenstien, Ronny Ronen
Life of this patent
Estimating the term…
Abstract
A system and corresponding method use a PAUSE instruction as a low power hint in a single threaded or multithreaded environment using “processor slow mode.” One embodiment actually lowers the frequency of the processor clock. Another embodiment virtually lowers the frequency of the processor clock by gating M clock cycles out of every N clock cycles. When all threads have issued a PAUSE instruction, the processor enters slow mode and remains there for a while. After this while, the processor returns to normal mode. Alternatively, an event, such as an interrupt or an exception, can cause the processor to return to normal mode from slow mode.
Claims46
An apparatus, comprising:
- a machine-readable medium having machine-readable instructions stored thereon to cause a processor to:
- determine that each thread running on the processor has issued a pause instruction;
- and
- reduce power consumption in response to the determination that each thread running on the processor has issued a pause instruction.
A method, comprising:
- determining that each thread running on a processor has issued a pause instruction;
- and
- leaving a normal mode of operation and entering into a slow mode of operation in response to the determination that each thread running on the processor has issued a pause instruction.
An apparatus comprising:
- a processor having:
- front-end logic to receive instructions;
- and
- power conservation logic coupled to the front-end logic to reduce power consumption of the processor in response to the front-end logic receiving a pause instruction from each thread operating in the processor.
An apparatus, comprising:
- a processor having:
- first logic to determine that each thread running on the processor has issued a pause instruction;
- and
- second logic coupled to the first logic to reduce power consumption in response to the determination that each thread running on the processor has issued a pause instruction.
An apparatus comprising:
- a processor having:
- first logic to determine that each thread running on the processor has issued a pause instruction;
- and
- second logic coupled to the first logic to cause the processor to enter into a slow mode of operation in response to the determination that each thread running on the processor has issued a pause instruction to indicate that the thread is paused.
An apparatus, comprising:
- a processor having:
- first logic to receive instructions;
- and
- second logic coupled to the first logic to hint the processor to enter a low power mode in response to the first logic receiving a pause instruction from each thread operating in the processor.
Dependencies are inferred from the claim text.