A method for allowing a data processing unit to repeat a sequence of instruction execution sets to be repeated N times, the data processor having a pipelined architecture, at least one data arithmetic unit and a program sequencer, the method comprising the following steps:
- fetching instruction fetch sets, the instruction fetch sets having at least one instruction to be executed by at least one data arithmetic unit;
- dispatching each instruction out of a first instruction execution set to an appropriated data arithmetic unit, wherein if the first instruction execution set has a first prefix instruction, dispatching the first prefix instruction to the program sequencer;
- wherein the first instruction execution set is a subset of the instruction fetch set;
- and
- executing each instruction by the appropriate data arithmetic units, wherein if the first instruction execution set comprises the first prefix instruction, determining whether a loop was iterated N times, and if the loop was not iterated N times initiating a first delayed jump operation to a first instruction execution set of the sequence of instruction execution sets, and
- if a second instruction execution set of the sequence of instruction execution sets scheduled after the first instruction execution set and before the first delayed jump operation comprises a second prefix instruction initiating a second delayed jump operation performing the second delayed jump operation only when the first delayed jump operation is not performed.