Parallel processing apparatus
AssigneeNEC Corporation
InventorSachiko Shimada
Life of this patent
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Abstract
Disclosed is a parallel processing apparatus capable of reducing power consumption by efficiently executing a fork instruction for activating a plurality of processors. The parallel processing apparatus has a processor element (10) for generating (forking) a thread consisting of a plurality of instructions of an external unit. The processor element comprises a fork-instruction predicting section (14) which includes a predicting section for predicting whether or not the fork condition of a fork-conditioned fork instruction is satisfied after fetching but before executing the instruction.
Claims76
A parallel processing apparatus having processing means for generating (forking) a thread consisting of a plurality of instructions on an external unit,
- said processing means including a predicting section for predicting whether or not a fork condition of a fork-conditioned fork instruction is satisfied after fetching but before executing said instruction.
A parallel processing apparatus comprising processing means having means for issuing an externally forked thread,
- said processing means including a predicting section predicting whether or not a thread-end condition of a thread-end-conditioned thread-end instruction for terminating said forked thread is satisfied after fetching but before executing said instruction.
A parallel processing apparatus comprising processing means for generating a thread consisting of a plurality of instructions on an external unit, said processing means including:
- means for issuing an externally forked thread;
- and
- a predicting section for predicting of whether or not a fork condition of a fork-conditioned fork instruction is satisfied after fetching but before executing said fork instruction and whether or not a thread-end condition of a thread-end-conditioned thread-end instruction for terminating said forked thread is satisfied after fetching but before executing said thread-end instruction.
A parallel processing apparatus comprising:
- analysis means for analyzing an input instruction;
- prediction means for, when said instruction analyzed by said analysis means is a fork-conditioned fork instruction, predicting whether or not a fork condition of said fork-conditioned fork instruction is satisfied after fetching but before executing said instruction and sending out a fork instruction in accordance with a result of said prediction;
- and
- execution means for executing said instruction, deciding whether or not said prediction of said fork instruction is correct, and sending out an instruction to cancel a thread generated by said fork instruction, when said fork instruction has been sent out and said prediction is wrong.
A parallel processing apparatus comprising:
- analysis means for analyzing an input instruction;
- prediction means for, when said instruction analyzed by said analysis means is a thread-end-conditioned thread-end instruction for terminating a forked thread, predicting whether or not a thread-end condition of said thread-end-conditioned thread-end instruction is satisfied after fetching but before executing said instruction and sending out a thread-end instruction in accordance with a result of said prediction;
- and
- execution means for executing said instruction, deciding whether or not said prediction of said thread-end instruction is correct, and sending out an instruction to cancel stopping of a thread which has been stopped by said thread-end instruction, when said thread-end instruction has been sent out and said prediction is wrong.
Dependencies are inferred from the claim text.