Maintaining processor ordering by checking load addresses of unretired load instructions against snooping store addresses
AssigneeIntel Corporation
InventorsMuntaquim F. Chowdhury, Douglas M. Carmean
Life of this patent
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Abstract
An apparatus in a first processor includes a first data structure to store addresses of store instruction dispatched during a last predetermined number of cycles. The apparatus further includes logic to determine whether a load address of a load instruction being executed matches one of the store addresses in the first data structure. The apparatus still further includes logic to replay to the respective load instruction if the load address of the respective load instruction matches of the store addresses in the first data structure.
Claims14
A method comprising:
- maintaining load addresses of load instructions that have not been retired in a load buffer of a first processor;
- snoping the load buffer to determine whether a store address of a store instruction being dispatched matches one of the load addresses in the load buffer of the first processor,
- aborting a speculative state of the first processor in response to a match between the store address associated with the store instruction and one of the load addresses in the load buffer;
- maintaining store addresses of the store instructions dispatched during a last predetermined number of cycles in a first data structure of the first processor;
- in response to a load instruction being executed, determining whether a load address of the load instruction being executed matches one of the store addresses in the first data structure;
- and
- replaying the load instruction if the load address of the load instruction matches one of the store addresses in the first data structure.
An apparatus in a first processor comprising:
- a load buffer to a store load addresses of a load instructions that have not been retired;
- logic to determine whether a store address of a store instruction being dispatched matches one of the load addresses in the load buffer of the first processor;
- logic to abort a speculative state of the first processor in response to a match between the store address of the store instruction and one of the load addresses in the load buffer;
- a first data structure to maintain store addresses of store instructions being dispatched during a last predetermined number of cycles;
- logic to determine whether a load address of a load instruction being executed matches one of the store addresses in the first data structure;
- and
- logic to replay the load instruction if the load address of the load instruction matches one of the store addresses in the first data structure.
An apparatus in a first processor comprising:
- a first data structure to store addresses of store instructions dispatched during a last predetermined number of cycles;
- logic to determine whether a load address of a load instruction being executed matches one of the store addresses in the first data structure;
- and
- logic to replay to the respective load instruction if the load address of the respective load instruction matches of the store addresses in the first data structure.
A method comprising:
- storing addresses of store instructions dispatched by a first processor during a last predetermined number of cycles in a first data structure;
- determining whether a load address of a load instruction being executed matches one of the store addresses in the first data structure;
- and
- replaying to the respective load instruction if the load address of the respective load instruction matches of the store addresses in the first data structure.
Dependencies are inferred from the claim text.