Multi-channel DMA with request scheduling

A digital system, comprising:

• a plurality of requestor circuits each having at least one request address output node for providing a request address and at least one request output, at least one of the plurality of requestor circuits comprises address generation circuitry for forming a sequence of request addresses as part of a single request;
• a port circuit with a plurality of request address input nodes connected respectively to the request address output nodes of the plurality of requestor circuits, a memory address output node for providing a memory address selected from the plurality of request address output nodes to a memory resource, and a scheduler circuit operable to select a next request that will be served by the port, wherein after one of the sequence of request addresses from said at least one of the plurality of requestor circuits is selected by the port circuitry a next sequential request address is provided to the port circuitry A the at least one requestor and wherein the scheduler circuit comprises:
• an allocation circuit with a plurality of request inputs each connected to a respective request output on the plurality of requestor circuits, the allocation circuit operable to select a subset of requests from the plurality of request inputs;
• and
• an interleaver circuit coupled to the allocation circuit, the interleaver circuit operable to select the next request from among the subset of request signals that will be served next by the port circuit, wherein the port circuit is operable to select one of the plurality of request address input nodes for receiving a request address in response to the next request selected by the interleaver circuit.

A method of operating a digital system having a memory resource and a plurality of requestor circuits which each require access to the memory resource, comprising the steps of:

• receiving a plurality of requests on a respective plurality of buses from the plurality of requestor circuits, at least one of the plurality of requestor circuits comprises address generation circuitry for forming a sequence of request addresses as part of a single request;
• allocating a subset of requests from the plurality of requests and storing the subset of requests in a request allocation table;
• interleaving the subset of requests from the request allocation table to determine the next request that will be presented to the memory resource;
• receiving a next sequential request address from the at least one of the plurality of requestor circuits after one of the sequence of request addresses has been presented to the memory resource.