Data processing system and method of communication that reduce latency of write transactions subject to retry

#1. Technical Field

#The present invention relates in general to data processing and, in particular, to memory access in a data processing system. Still more particularly, the present invention relates to a data processing system and method of communication that reduce latency of write transactions subject to retry.

#2. Description of the Related Art

#The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

#FIG. 1 depicts an illustrative embodiment of a data processing system with which the method and system of the present invention may advantageously be utilized;

#FIG. 2 illustrates a cache in accordance with an illustrative embodiment of the present invention;

#With reference now to the figures and in particular with reference to FIG. 1, there is illustrated a high-level block diagram of a symmetric multiprocessor (SMP) data processing system in accordance with the present invention. As depicted, data processing system 8 includes a number of processing units 10a-10n (e.g., n=64) coupled to a system interconnect 12. Each processing unit 10 is an integrated circuit including one or more processors 14. In addition to the registers, instruction flow logic and execution units utilized to execute program instructions, each of processors 14 also includes an associated level one (L1) cache 16, which temporarily stores data that are likely to be accessed by the associated processor 14. Although L1 caches 16 are illustrated in FIG. 1 as unified caches, those skilled in the art will appreciate that each of L1 caches 16 could alternatively be implemented as bifurcated instruction and data caches.

#As further illustrated in FIG. 1, the memory hierarchy of data processing system 8 also includes one or more system memories 22, which form the lowest level of volatile data storage in the memory hierarchy, and one or more lower levels of cache memory, such as on-chip level two (L2) caches 18, which are utilized to stage data from system memory 22 to processors 14. As understood by those skilled in the art, each succeeding lower level of the memory hierarchy is typically capable of storing a larger amount of data than higher levels, but at higher access latency. For example, in an exemplary embodiment, L1 caches 16 may each have 512 64-byte cache lines for a total storage capacity of 32 kilobytes (kB), all at single cycle latency. L2 caches 18 may each have 2048 128-byte cache lines for a total storage capacity of 256 kB at approximately 10-cycle latency. Finally, each system memory 22 can store hundreds of megabytes or gigabytes of data at an even longer latency, for example, 300-400 cycles.

#Data processing system 8 further includes a memory controller 20 that interfaces system memory 22 to interconnect 12. Memory controller 20 includes one or more queues 21 having one or more individual queue entries 23. Queue entries 23 are utilized by memory controller 20 to buffer transactions (e.g., read, write, etc.) snooped on interconnect 12 until processing of the transactions is completed. As shown, data processing system 8 may also include other snoopers, such as I/O controller 26, which interfaces one or more I/O devices 28 to interconnect 12.