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US 6,687,791 B2Granted
Shared cache for data integrity operations
AssigneeSun Microsystems, Inc.
InventorJohn M. Morrison
Life of this patent
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AssigneeSun Microsystems, Inc.
InventorJohn M. Morrison
Estimating the term…
Various embodiments of a method and system for sharing a cache such as an on-chip L1 cache are disclosed. In one embodiment, a processing device includes a shared cache and a plurality of processors that are each coupled to the shared cache and each configured to store the result of a data integrity operation in the shared cache. Each of the processors performs the same data integrity operation on the same data to generate its result. Because the results are stored in the shared cache, a first processor may quickly access and operate on the results. In one embodiment, the first processor may perform a comparison operation or voting operation on the results stored in the shared cache.
A data processing system comprising:
A processing device comprising:
A method of sharing a shared cache between multiple processors, the method comprising:
A processing device comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Error detection or correction of the data by redundancy in hardware: using passive fault-masking of the redundant circuits
Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's: to protect a block of data words, e.g. CRC or…
Error detection by comparing the output of redundant processing systems: using additional compare functionality in one or some but not all of the…
Multiuser, multiprocessor or multiprocessing cache systems: with a shared cache
Term ended 19 Apr 2022 (estimated)
1. Field of the Invention
This invention relates to error detection in storage systems.
2. Description of the Related Art
A better understanding of the present invention can be obtained when the following detailed description is considered in conjunction with the following drawings, in which:
FIG. 1 illustrates one embodiment of a data processing system;
FIG. 2 shows an example of checksums that may be used in some embodiments of a storage array;
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.
Storage System
FIG. 1 shows a functional block diagram of one embodiment of a data processing system 100 that may include an embodiment of a data integrity device. Data processing system 100 includes a host 101 connected to a storage system 150 via host/storage connection 132. Host 101 may include one or more processors and various I/O devices such as a monitor, keyboard, mouse, etc. (not shown). System memory to temporarily store data and software instructions may also be provided in host 101. Host 101 may be coupled to host/storage connection 132 by an I/O bus such as a PCI (Peripheral Component Interconnect) bus. In one embodiment, data processing system 100 may be configured as a SAN (Storage Area Network).