Cache which provides partial tags from non-predicted ways to direct search if way prediction misses

A processor comprising:

• a line predictor configured to provide a way prediction responsive to a fetch address;
• and
• an instruction cache coupled to receive said way prediction and said fetch address, wherein said instruction cache is set associative and includes a tag array configured to output a plurality of partial tags responsive to an index of said fetch address, and wherein said instruction cache is configured, responsive to said fetch address missing in a first way identified by said way prediction, to search a second way of said tag array for which a corresponding partial tag of said plurality of partial tags matches a corresponding portion of said fetch address.

A cache comprising:

• a tag array coupled to receive an index of an address and a way prediction, wherein the tag array comprises a plurality of ways, and wherein the way prediction identifies a predicted way of the plurality of ways, and wherein the tag array is configured to output a plurality of partial tags, and wherein each of the plurality of partial tags corresponds to one of the plurality of ways;
• and
• a control circuit coupled to the tag array, wherein the control circuit is configured to generate a search way indication identifying a search way responsive to the address missing in the predicted way, and wherein the search way is a non-predicted way of the plurality of ways, and wherein a first partial tag corresponding to the search way matches a corresponding portion of the address.