Method and implementation for addressing and accessing an expanded read only memory (ROM)

In a data processing system comprising a processor coupled to a Read Only Memory (ROM) via an address bus for output of bus addresses corresponding to ROM data storage locations, the ROM having a number of addresses greater than the finite address capacity of the address bus, the processor coupled to the ROM via a data bus for receiving from the ROM stored data identified by the ROM addresses, a method for expanding the number of accessible ROM addresses beyond the finite address bus capacity said method comprising the steps of:

• allocating a first portion of the bus addresses as random reading mode bus addresses for randomly addressing the ROM for reading data, the random reading mode bus addresses having direct correspondence with ROM addresses;
• allocating a second portion of bus addresses as sequential reading mode bus addresses for addressing the ROM in sequential ROM address order for reading data;
• associating at least one of the sequential reading mode bus addresses with a plurality of sequentially numbered ROM addresses;
• and
• loading the first numbered address of the plurality of sequentially numbered ROM addresses as data into at least one counter;
• wherein processor output of the associated sequential reading mode address effectuates application of the contents of the counter as an address to the ROM and increments the counter;
• wherein the loading step comprises:
• generating a write enable signal;
• outputting, to the address bus, the sequential reading mode bus address associated with the counter;
• outputting, as data to the data bus, the first numbered address of the plurality of sequentially numbered ROM addresses;
• and
• writing the data output as contents to the at least one counter.

In a data processing system comprising a processor coupled to a Read Only Memory (ROM) via an address bus, the ROM having an address capacity greater than the address capacity of the address bus, a method for addressing the ROM comprising a random address mode in which the processor outputs a first address that directly corresponds to a ROM address and a sequential address mode in which the processor outputs a second address that corresponds to a plurality of ROM addresses, the method comprising the steps of:

• in response to output by the processor of the first address, applying the first address as an address to the ROM in the random address mode;
• and
• in response to output by the processor of the second address, applying a counter output as an address to the ROM in the sequential address mode;
• wherein the counter comprises a plurality of interconnected counter stages and each of a plurality of unique processor output addresses is related respectively to one of the counter stages, and said sequential access mode further comprises:
• decoding a generated output from the processor of one of the unique processor output addresses;
• in response to the decoding step, applying the contents of all of the counter stages as an address to the ROM;
• and
• incrementing the counter.

In a data processing system comprising a processor having a total number of address output terminals and an address bus having a bit width corresponding to a finite address capacity, the bit width equal in number to the total number of processor address output terminals, the processor coupled to a Read Only Memory (ROM) via an address bus, the ROM having an address capacity greater than the address capacity of the address bus, a method for addressing the ROM comprising a random address mode in which the processor outputs a first address that directly corresponds to a ROM address and a sequential address mode in which the processor outputs a second address that corresponds to a plurality of ROM addresses, the method comprising the steps of:

• applying an address output by the processor to a decoder to determine whether the sequential address operational mode or the random address operational mode is identified;
• in response to identification of the sequential address operational mode in the applying step, activating a counter associated with the decoded output to apply the contents of the counter as a ROM address;
• and
• in response to identification of the random address operational mode in the applying step, applying the address output by the processor as a ROM address.

In a data processing system comprising a processor coupled to a Read Only Memory (ROM) via an address bus, the ROM having an address capacity greater than the address capacity of the address bus, a method for addressing the ROM comprising a random address mode in which the processor outputs a first address that directly corresponds to a ROM address and a sequential address mode in which the processor outputs a second address that corresponds to a plurality of ROM addresses, the method comprising the steps of:

• applying an address output by the processor to a decoder to determine whether the sequential address operational mode or the random address operational mode is identified;
• in response to identification of the sequential address operational mode in the applying step, activating a counter associated with the decoded output to apply the contents of the counter as a ROM address;
• and
• in response to identification of the random address operational mode in the applying step, applying the address output by the processor as a ROM address;
• wherein the counter comprises a plurality of interconnected counter stages, each counter stage having an output connected to the multiplexer, and the step of applying comprises:
• coupling the address output by the processor to a plurality of decoders, each decoder associated with a respective one of the counter stages;
• and
• in response to determination of a sequential address operational mode by one of the decoders, applying the contents of all of the counter stages as ROM address to the ROM through the multiplexer.

A data processing system for addressing an expanded Read Only Memory (ROM) to access data stored therein in either a random address access mode or a sequential address access mode, said system comprising:

• a processor connected to the ROM by a data bus, the processor having, a total number of address output terminals;
• an address bus connected to the processor for output therefrom of addresses corresponding to stored ROM data to be accessed, the address bus having a bit width equal in number to the total number of processor address output terminals, the processor and address bus having a smaller bus address output capacity than the number of addresses in the ROM;
• a multiplexer having a plurality of inputs, a first multiplexer input connected to the address bus, and a multiplexer output connected to the ROM to apply ROM addresses thereto;
• and
• a decoder having an input connected to the address bus and an output coupled to a counter, the counter having an output connected to a second input of the multiplexer;
• wherein the multiplexer is responsive to an output signal of the decoder indicative of the sequential address access mode to apply the counter output to the multiplexer output as a ROM address and, in the absence of the decoder output signal, to preclude application of counter output to the ROM.

A data processing system for addressing an expanded Read Only Memory (ROM) to access data stored therein in either a random address access mode or a sequential address access mode, said system comprising:

• a processor connected to the ROM by a data bus;
• an address bus connected to the processor for output therefrom of addresses corresponding to stored ROM data to be accessed, the processor and address bus having a smaller bus address output capacity than the number of addresses in the ROM;
• a multiplexer having a plurality of inputs, a first multiplexer input connected to the address bus, and a multiplexer output connected to the ROM to apply ROM addresses thereto;
• and
• a decoder having an input connected to the address bus and an output coupled to a counter, the counter having an output connected to a second input of the multiplexer;
• wherein the multiplexer is responsive to an output signal of the decoder indicative of the sequential address access mode to apply the counter output to the multiplexer output as a ROM address and, in the absence of the decoder output signal, to preclude application of counter output to the ROM;
• and
• wherein the counter comprises a plurality of interconnected counter stages, each having inputs connected to the data bus and outputs connected to the multiplexer, and further comprising:
• a plurality of decoders, each having an input connected to the address bus and an output coupled to a respective one of the counter stages;
• and
• a logic circuit having input connections to the decoders and the processor and having output connections to the counters and the multiplexer.