Method and apparatus for transmitting control information across a serialized bus interface

A method of communicating from a processor to a peripheral device, the method comprising:

• communicating from the processor an indication that the system is being reset, the indication being communicated along at least one line of a parallel bus;
• receiving the indication at a first interface device;
• communicating the indication from the interface device and along a serial link using control codes of an encoding/decoding scheme of the interface device;
• receiving the indication at a second interface device, the second interface device coupled to the first interface device through the serial link;
• and communicating a confirmation from the second interface device to the first interface device, the confirmation indicating that the indication from the first interface device has been received,
• wherein the confirmation comprises a sequence of control codes of the encoding/decoding scheme, at least a portion of the confirmation sequence being an inverted copy of a sequence of control codes communicate the indication from the first interface device.

A method of communicating from a processor to a peripheral device, the method comprising:

• communicating from the processor an indication that the system is being reset, the indication being communicated alone at least one line of a parallel bus;
• receiving the indication at a first interface device;
• communicating the indication from the interface device and alone a serial link using control codes of an encoding/decoding scheme of the interface device;
• and
• receiving the indication at a second interface device, the second interface device coupled to the first interface device through the serial link,
• wherein communicating the indication includes communicating information relating to a mode of operation.

A computer system comprising:

• a processor;
• a memory system coupled to the processor through a processor bus;
• a first bridge circuit coupled between the processor bus and a first expansion bus;
• a plurality of peripheral devices coupled to the first expansion bus;
• a first interface device coupled to the first expansion bus, the first interface device including a plurality of parallel data output nodes and at least two control output nodes;
• a first transceiver device with data inputs coupled to the data output nodes and with at least two control input nodes coupled to the at least two control output nodes of the first interface device;
• a serial link;
• a second transceiver device coupled to the first transceiver device by the serial link;
• a second interface device coupled between the second transceiver device and a second expansion bus;
• and
• at least one additional peripheral device coupled to the second expansion bus;
• wherein the first and second interface devices each include data control circuitry utilizing a coding scheme to generate one of a set of control codes to be provided to the at least two control output nodes;
• wherein the first interface device includes reset control circuitry generating a specified sequence of control codes on the at least two control outputs to communicate information from the first interface device to the second interface device, the information relating to a state of the second expansion bus;
• wherein the first and second transceivers both utilize an 8B/10B encoding/decoding scheme to communicate data across the serial link;
• wherein the specified sequence of control codes comprises a sequence of Idle and Extend codes;
• and
• wherein the specified sequence of control codes is used to communicate information that the second expansion bus should be reset.

A computer system comprising:

• a processor;
• a memory system coupled to the processor through a processor bus;
• a first bridge circuit coupled between the processor bus and a first expansion bus;
• a plurality of peripheral devices coupled to the first expansion bus;
• a first interface device coupled to the first expansion bus, the first interface device including a plurality of parallel data output nodes and at least two control output nodes;
• a first transceiver device with data inputs coupled to the data output nodes and with at least two control input nodes coupled to the at least two control output nodes of the first interface device;
• a serial link;
• a second transceiver device coupled to the first transceiver device by the serial link;
• a second interface device coupled between the second transceiver device and a second expansion bus;
• and
• at least one additional peripheral device coupled to the second expansion bus;
• wherein the first and second interface devices each include data control circuitry utilizing a coding scheme to generate one of a set of control codes to be provided to the at least two control output nodes;
• wherein the first interface device includes reset control circuitry generating a specified sequence of control codes on the at least two control outputs to communicate information from the first interface device to the second interface device, the information relating to a state of the second expansion bus;
• wherein the first and second transceivers both utilize an 8B/10B encoding/decoding scheme to communicate data across the serial link;
• wherein the specified sequence of control codes comprises a sequence of Idle and Extend codes;
• wherein the specified sequence of control codes is used to communicate information that the second expansion bus should be reset;
• and
• wherein the specified sequence of control codes is used to communicate information that the second expansion bus should be reset into a one of a plurality of modes.

A computer system comprising:

• a processor;
• a memory system coupled to the processor through a processor bus;
• a first bridge circuit coupled between the processor bus and a first expansion bus;
• a plurality of peripheral devices coupled to the first expansion bus;
• a first interface device coupled to the first expansion bus, the first interface device including a plurality of parallel data output nodes and at least two control output nodes;
• a first transceiver device with data inputs coupled to the data output nodes and with at least two control input nodes coupled to the at least two control output nodes of the first interface device;
• a serial link;
• a second transceiver device coupled to the first transceiver device by the serial link;
• a second interface device coupled between the second transceiver device and a second expansion bus;
• and
• at least one additional peripheral device coupled to the second expansion bus;
• wherein the first and second interface devices each include data control circuitry utilizing a coding scheme to generate one of a set of control codes to be provided to the at least two control output nodes;
• wherein the first interface device includes reset control circuitry generating a specified sequence of control codes on the at least two control outputs to communicate information from the first interface device to the second interface device, the information relating to a state of the second expansion bus;
• wherein the first and second transceivers both utilize an 8B/10B encoding/decoding scheme to communicate data across the serial link;
• wherein the specified sequence of control codes comprises a sequence of Idle and Extend codes;
• wherein the second interface device includes confirmation circuitry generating a confirmation sequence of control codes, the confirmation sequence to be communicated to the first interface device through the serial link;
• and
• wherein a portion of the confirmation sequence comprises an inverted version of the specified sequence.

A computer system comprising:

• a processor;
• a memory system coupled to the processor through a processor bus;
• a first bridge circuit coupled between the processor bus and a first expansion bus;
• a plurality of peripheral devices coupled to the first expansion bus;
• a first interface device coupled to the first expansion bus, the first interface device including a plurality of parallel data output nodes and at least two control output nodes;
• a first transceiver device with data inputs coupled to the data output nodes and with at least two control input nodes coupled to the at least two control output nodes of the first interface device;
• a serial link;
• a second transceiver device coupled to the first transceiver device by the serial link;
• a second interface device coupled between the second transceiver device and a second expansion bus;
• and
• at least one additional peripheral device coupled to the second expansion bus;
• wherein the first and second interface devices each include data control circuitry utilizing a coding scheme to generate one of a set of control codes to be provided to the at least two control output nodes;
• wherein the first interface device includes reset control circuitry generating a specified sequence of control codes on the at least two control outputs to communicate information from the first interface device to the second interface device, the information relating to a state of the second expansion bus;
• wherein the first and second transceivers both utilize an 8B/10B encoding/decoding scheme to communicate data across the serial link;
• wherein the specified sequence of control codes comprises a sequence of Idle and Extend codes;
• and
• wherein the first expansion bus operates at a first clock rate and wherein the information relating to a state of the second expansion bus is communicated from the first interface device to the second interface device at a second clock rate that is faster than the first clock rate.