Serial peripheral interface with high performance buffering scheme

#The present invention relates to a serial peripheral interface for use in microcontroller-based products. More particularly, the present invention relates to a high performance buffering scheme for a serial peripheral interface that facilitates high data transmission rates between microprocessors, components and other devices.

#The demand for higher performance, microcontroller-based products for use in communication and processing applications continues to increase rapidly. As a result, microcontroller-based product manufacturers are requiring for the components and devices within these products to be continually improved to meet the design requirements of a myriad of emerging audio, video and imaging applications.

#These microcontroller-based products use various types of processors, for example, general purpose microprocessors for controlling the logic of various digital devices, such as clock radios, microwave ovens, digital video recorders and the like, and special purpose microprocessors, such as math coprocessors for mathematical computations, or digital signal processors used in manipulating various types of information, including sound, imaging and video information. For the transmitting and receiving of data between various devices and components, microprocessors and other devices utilize various types of serial interfaces. One such type of interface definition typically used is the serial peripheral interface (SPI). In addition, for the temporary storage of data, for example, to permit the microprocessors to manipulate the data before transferring the data through the SPI to another device, the microprocessors generally utilize one or more buffers. These buffers are configured with the SPI's to enable the processors to transmit and receive data to and from the buffers as needed in an application.

#A more complete understanding of the present invention may be derived by referring to the detailed description and claims when considered in connection with the Figures, where like reference numbers refer to similar elements throughout the Figures, and:

#FIG. 1 illustrates a block diagram of a prior art serial peripheral interface for master and slave devices;

#FIG. 2 illustrates a block diagram of a prior art double buffering scheme for a serial peripheral interface;

#The present invention may be described herein in terms of various functional components and various processing steps. It should be appreciated that such functional components may be realized by any number of hardware or structural components configured to perform the specified functions. For example, the present invention may employ various integrated components, e.g., buffers, voltage and current references, memory components and the like, comprised of various electrical devices, e.g., resistors, transistors, capacitors, diodes or other devices, whose values may be suitably configured for various intended purposes. In addition, the present invention may be practiced in any microcontroller-based application. Such general applications that may be appreciated by those skilled in the art in light of the present disclosure are not described in detail herein. However for purposes of illustration only, exemplary embodiments of the present invention will be described herein in connection with a SPI interface for a master device, such as a microprocessor, or a slave device, such as an A/D converter. Further, it should be noted that while various components may be suitably coupled or connected to other components within exemplary circuits, such connections and couplings can be realized by direct connection between components, or by connection through other components and devices located therebetween.

#As discussed above, previous attempts for providing serial peripheral interfaces configured for high data rates have generally included the use of larger buffers, e.g., double buffer configurations, and have resulted in increased logic area, higher power consumption, and higher CPU overhead. However, in accordance with the present invention, a serial peripheral interface (SPI) has been configured with a high performance buffering scheme that suitably provides a high data rate without increasing the logic area, power consumption and CPU overhead required.

#In accordance with an exemplary embodiment of the present invention, a serial peripheral interface comprises a single buffer configuration. While the single buffer can comprise various arrangements, in accordance with an exemplary embodiment, the single buffer comprises a queuing configuration. For example, the single buffer can be configured in a circular configuration, such as, for example, a first in/first out (FIFO) buffer as illustrated below in an exemplary embodiment. Further, the single buffer can be configured in a linear queuing configuration. Moreover, the size of the single buffer can comprise any number of bytes, depending on any given design criteria. Further, the single buffer can be suitably configured in any other queuing configuration, now known or hereinafter devised.