Efficient direct memory access transfer of data and check information to and from a data storage device

#This invention relates to computer systems; more particularly, to methods and apparatus for transferring data and check information between computer main memory and data storage devices by means of direct memory access.

#Computer direct access data storage devices are typically organized into fixed-size blocks of data storage. For example, a computer disk drive may organize data storage into a number of blocks of data, each block holding 512 bytes of data, and each block having a unique logical block address, with the blocks being sequentially numbered starting with block zero. Other block addressing methods are also in use, including specifying cylinders, tracks, and sectors; but again, each block has a unique address, and the blocks are considered to appear on the device in a well-defined logical order. Other storage media such as tapes may also be organized into fixed-size blocks, depending on the application.

#A substantial portion of the work carried out by a computer system is the storage and retrieval of data to and from data storage devices (I/O). In early computer systems this work was carried out by the central processing unit (CPU), requiring the use of a substantial portion of the CPU's available computing capacity to perform the detailed steps of the I/O. However, in modern systems the mechanics of data transfer to and from storage devices is often carried out by a separate direct memory access (DMA) controller. FIG. 1A shows a simplified block diagram of such a system, shown at 101. System 101 has a CPU 103, main memory 105, DMA controller 107, storage medium 109, and communication bus 111. In systems like 101, to initiate the I/O data transfer, CPU 103 programs DMA controller 107 with the information it requires, and issues a command (via communication bus 111) to begin the transfer. The CPU can then attend to other computations while the DMA controller carries out the detailed steps of the transfer. Thus, DMA controller 107 serves as an intermediary between main memory 105 and storage medium 109. When the I/O operation is complete, CPU 103 is informed of the I/O completion by DMA controller 107, whereupon the CPU may make use of the results of the transfer. In this way, most of the work required to carry out the I/O is offloaded from the CPU, thus freeing the CPU to carry out other work. For example, the CPU may perform processes such as interchange with main memory 105.

#The following detailed description can be more fully understood when considered in conjunction with the drawings in which:

#FIG. 1A is a simplified block diagram showing the mechanics of data transfer to and from storage devices using a separate direct memory access (DMA) controller.

#FIG. 1B is a simplified block diagram illustrating a conventional mechanism for transferring data from a main memory to a storage medium via a DMA controller.

#In the following detailed description of the present invention, numerous specific embodiments are set forth in order to provide a thorough understanding of the invention. However, as will be apparent to those skilled in the art, the present invention may be practiced without these specific details or by using alternate elements or processes. In some descriptions herein, well-known processes, procedures, and components have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

#As mentioned, the invention provides efficient architectures and methods for using direct memory access (DMA) to store and retrieve data and associated check information in fixed-size blocks to and from a data storage device. This is accomplished by the use of interleave criteria, provided in registers in the DMA controller. Since fixed-sized storage blocks are specified, with a fixed data size and a fixed check information size per storage block, the interleave criteria can be represented in a form that is significantly more compact than would be the representation of the same interleave using a conventional scatter/gather list. In this invention, representation of the interleave criteria is constrained to fixed-sized blocks, including two segments (e.g. one of data and one of check information). The data and check information block sizes may be different from one another, but their respective sizes do not vary. Thus, for the specific example of interleaving data and check information, the interleave criteria for an entire transfer is represented in a small number of registers, independent of the total size of the transfer. Using a conventional scatter/gather list to express this same constrained interleave would require two scatter/gather list elements for each and every interleaved block (data and check information) involved in the transfer—large transfers would require an inordinate number of scatter/gather list elements.

#FIG. 2A is a simplified block diagram depicting a DMA controller architecture 201 and aspects of a method for a write operation in accordance with one embodiment of the invention. During a write “DMA transfer”, DMA controller 205 transfers data from main memory 203 to storage medium 207. In this example, main memory 203 contains two separate contiguous series of memory segments corresponding to data and its associated check information. More particularly, as shown, the first segment of memory includes data blocks, D0-D7, while the second segment of memory includes associated check information blocks, C0-C7. In one embodiment, the CPU computes the associated check information and stores it contiguously in main memory as C0-C7. DMA controller 205 transfers data blocks D0-D7 (4096 bytes of data) and its associated check information C0-C7 (64 bytes of data) from main memory 203 to storage medium 207. In the transfer process, the data and check information is preferably interleaved and stored as a contiguous set of data blocks B0-B7 (4160 bytes of data). The interleaving process will be discussed in more detail below with reference to FIG. 3A and FIG. 3B.