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US 6,687,763 B2Granted
ATAPI command receiving method
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsYoko Kimura, Yasushi Ueda
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AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsYoko Kimura, Yasushi Ueda
Estimating the term…
The present invention provides an ATAPI command receiving method in which the CPU 72 can quickly correspond to other processings without expending much time for capturing data, as well as it can be prevented that data which are being captured by the CPU should be destroyed. In this ATAPI command receiving method, when an ATAPI protocol control LSI 71 comprising a shared register storage area 711 (including a data FIFO 7112 for containing command packets) for receiving a command from the host computer via an ATA bus 2, and a buffer memory 712 which can be used as a RAM of a CPU 72 receives a command, shared register values (including a command packet value) are stored at a storage destination address in the buffer memory 712 which is designated by the CPU 72, when the data storage permission is given by the CPU 72.
A command receiving method in a device which comprises an LSI having a shared register storage area and a buffer memory and controlling an ATAPI (AT Attachment Packet Interface) protocol, and a CPU for executing control of the device having the LSI, wherein
A command receiving method in a device which comprises an LSI having a shared register storage area and a buffer memory and controlling an ATAPI (AT Attachment Packet Interface) protocol, and a CPU for executing control of the device having the LSI, wherein
A command receiving method in a device which comprises an LSI having a shared register storage area and a buffer memory and controlling an ATAPI (AT Attachment Packet Interface) protocol, and a CPU for executing control of the device having the LSI, wherein
Dependencies are inferred from the claim text.
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Using a secondary processor, e.g. coprocessor: for non-native instruction execution, e.g. executing a command; for Java instruction set
Computing and data processing
Term ended 4 Apr 2022 (estimated)
The present invention relates to a command receiving method of a LSI which controls an ATAPI (AT Attachment Packet Interface) protocol and, more particularly, to an ATAPI command receiving method which can reduce a processing time of a CPU.
ATAPI is a standard which is created by that the ATA standard for an interface between a host computer and an integral hard disk is expended for use in multi-media devices, and details thereof are determined by the X3T13 Committee.
Hereinafter, the prior art ATAPI command receiving method is described with reference to FIGS. 5 and 6.
FIG. 1 is a conceptual diagram showing a structure of a device which uses an ATAPI command processing method according to the present invention and the flow of the command in the device.
FIG. 2 is a diagram illustrating a construction of storage of shared register values in a buffer memory according to a first embodiment of the present invention.
FIG. 3 is a diagram illustrating a construction of storage of shared register values in a buffer memory according to a second embodiment of the present invention.
[Embodiment 1]
Hereinafter, an ATAPI command receiving method according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 2.
FIG. 1 is a diagram showing a structure of a device 7 which uses the ATAPI command processing method according to the first embodiment and the flow of the command in the device 7.