US 6,687,757 B1Granted

Packet processor

AssigneeFlextronics Semiconductor Inc.

InventorsYuval Ben-Ze'ev, Yossi Livshitz, Raan Kahn, Yeshayahu Mor

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Abstract

A Packet Processor for a communication apparatus, for processing received and transmitted data streams made of packets. Each packet includes a header and a payload section, which includes a receiving part, a transmitting part, a Backbone Bus for conveying management data, instructions and addresses between various components of the Packet Processor, and a timing and control unit for administering the operation of the Packet Processor, and for timing of using transmission slots for the transmit path. The receiving part includes a receiving PHY interface by which a flow of data stream is conveyed from a Modulator-Demodulator section of the modem to the Packet Processor. The receiving part further includes a receiving Tubular Bus which received the flow of data stream, conveyed from the modem to the Packet Processor, the receiving Tubular Bus conveys data, while processed, the direction from the receiving PHY interface to a host interface. The receiving part includes one or more processing units between sections of the first Tubular Bus for sequentially receiving portions of a data stream from a section of the Tubular Bus, processing it and outputting the processed data to a next section of the first Tubular Bus. The receiving part contains a FIFO storage unit before and a FIFO storage unit after any of the processing units on the receiving Tubular Bus, for providing a temporary storage for portions of the data stream, and a first host interface for receiving data from the receiving Tubular Bus and conveying it to a host. The transmitting part further includes a FIFO storage unit before and after any of the processing units on the second Tubular Bus, and a transmitting PHY interface for receiving processed data from the transmitting Tubular Bus and conveying it to a Modulator-Demodulator section.

A Packet Processor for a communication apparatus, for processing received and transmitted data streams made of packets, each packet mainly comprises a header and a payload section, comprising:

(A) A receiving part comprising:
(a) A receiving PHY interface by which a flow of data stream is conveyed from a Modulator-Demodulator section of a modem to the Packet Processor;
(b) A receiving Tubular Bus receiving the said flow of data stream which is conveyed from the Modulator-Demodulator section of the modem to the Packet Processor, said receiving Tubular Bus conveying data, while processed, in the direction from the said receiving PHY interface to a host interface;
(c) At least one processing unit between sections of the said receiving Tubular Bus for sequentially receiving portions of a data stream from a section of the receiving Tubular Bus, processing the same, and outputting the processed data to a next section of the said receiving Tubular Bus;
(d) One FIFO storage unit before and one FIFO storage unit after any of the said processing units on the receiving Tubular Bus, for providing a temporary storage for portions of the data stream;
and
(e) A first host interface for receiving data from the receiving Tubular Bus and conveying it to a host;
(B) A transmitting part comprising:
(f) A second host interface for receiving data from the host and conveying it to:
(g) A transmitting Tubular Bus for receiving the said flow of data stream which is conveyed from the host to the Packet Processor, said transmitting Tubular Bus conveying the data stream, while processed, in the direction from the said second host interface to a transmitting PHY interface;
(h) At least one processing unit between sections of the said transmitting Tubular Bus, for sequentially receiving portions of the data stream from a section of the transmitting Tubular Bus, processing the same, and outputting the processed data to the next section of the said transmitting Tubular Bus;
(i) One FIFO storage unit before and one FIFO storage unit after any of the said processing units on the transmitting Tubular Bus, for providing a temporary storage for portions of the data stream;
and
(j) A transmitting PHY interface for receiving processed data from the transmitting Tubular Bus and conveying the same to a Modulator-Demodulator section;
(C) A Backbone Bus for conveying management data, instructions, and addresses between various components of the Packet Processor;
and
(D) Timing and control means for administering the operation of the Packet Processor, and particularly the timing of using transmission slots for the transmit path.

14 more elements

Abstract

Claims36