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US 6,687,724 B1Granted
Information processor
AssigneeSony Corporation
InventorsYukihiko Mogi, Kazuhiko Nishibori
Life of this patent
Estimating the term…
Abstract
An information processor 1 used as a processor in a personal computer for example includes an inner-product operational unit 3 which effects an SIMD type inner-product operation. The result of the inner-product operation effected in the inner-product operational unit 3 is stored into a P register 15 in the form of a word. A shift and shifting unit 16 reads the result of the inner-product operation stored in the P register 15, shifts the result by an arbitrary number of bits and then clips it with the arbitrary number of bits, and stores the result into a Y register 17 as a sub-word.
Claims21
An information processor comprising:
- an arithmetic circuit to provide a result of arithmetic operation in units of a word length;
- an intermediate register to store the result of arithmetic operation supplied from the arithmetic circuit;
- a shifting circuit to shift the data stored in the intermediate register by an arbitrary number of bits;
- a clipping circuit to clip the data shifted by the shifting circuit to an arbitrary bit length;
- and
- an output register to store as a sub-word the data clipped by the clipping circuit and sequentially shift the existing data therein by one sub-word from the higher to lower bits each time a data is entered for storage as a sub-word.
3 more elements
An information processor comprising:
- an input register to store a source data divided in sub-words;
- a coefficient register to store a coefficient data divided in sub-words;
- an inner-product operational unit to effect an inner-product operation of the source data stored in the input register and coefficient data stored in the coefficient register, in units of a sub-word, and provide the result of the operation in units of a word length;
- an intermediate register to store the result of the operation effected in the inner-product operational unit;
- a shifting unit to shift the data stored in the intermediate register by an arbitrary number of bits;
- a clipping circuit to clip the data of which the bit positions have been shifted by the shifting circuit to an arbitrary bit length;
- and
- an output register to store as a sub-word the data clipped by the clipping circuit, and sequentially shift the existing data therein by one sub-word from the higher to lower bits each time a data is entered for storage as a sub-word.
5 more elements
An information processor, comprising:
- an arithmetic circuit to provide the result of an arithmetic operation in units of a word length, the arithmetic circuit having an inner-product operational unit and an arithmetic logic unit (ALU);
- and
- an output register to store the result of the arithmetic operation effected in the arithmetic circuit as a sub-word and sequentially shift the existing data therein from the higher to lower bits in units of a sub-word each time a data is entered for storage as a sub-word;
- an input register to store a source data divided in sub-words;
- and
- a coefficient register to store a coefficient data divided in sub-words;
- the inner-product operational unit effecting an SIMD (single instruction multiple data stream) type inner-product of the source data stored in the input register and coefficient data stored in the coefficient register in sub-words.
4 more elements
An information processor comprising:
- an arithmetic circuit to provide the result of an arithmetic operation in units of a word length, the arithmetic circuit having an inner-product operational unit and an arithmetic logic unit (ALU);
- an output register to store the result of the arithmetic operation effected in the arithmetic circuit as a sub-word and sequentially shift the existing data therein from the higher to lower bits in units of a sub-word each time a data is entered for storage as a sub-word;
- and
- a data transfer path from the output register to the input register of the arithmetic logic unit.
1 more element
An information processor comprising:
- an input register to store a source data divided in sub-words;
- a coefficient register to store a coefficient data divided in sub-words;
- an inner-product operational unit to effect an SIMD type inner-product operation, in units of a sub-word, of the source data stored in the input register and coefficient data stored in the coefficient register, and provide the result of the SIMD type inner product operation in units of a word length;
- and
- an output register to store as a sub-word the result of the SIMD type inner-product operation effected in the inner-product operational unit and sequentially shift the existing data therein from the higher to lower bits in units of a sub-word each time a data is entered for storage as a sub-word.
2 more elements
Dependencies are inferred from the claim text.