US 6,687,722 B1Granted

High-speed/low power finite impulse response filter

AssigneeAgere Systems Inc.

InventorsPatrik Larsson, Christopher John Nicol

Life of this patent

Estimating the term…

Loading patent…

Abstract

A partial carry-save format is employed for a finite impulse response filter output representation, thereby reducing a number of flip-flops and hence power. By replacing the least significant bit processing section on the output side of the finite impulse response filter with a combined carry-save adder and carry-propagate adder followed by a register rather than two flip-flops, the load on the clock can be reduced, thereby achieving reduced propagation delay. To further improve the performance of the finite impulse response filter, a simpler carry-save adder is employed in the least significant bit section, which is possible due to the use of a single register at an input to each of the carry-save adders rather than two flip-flops, one for a carry output and one for a sum output from the adder. The combination of a reduction of half of the flip-flops and a replacement of a simpler carry-save adder for each of the carry-save adders results in a significant improvement in the overall filter performance and power and space consumption.

Claims21

Dependent claims

An apparatus comprising:

a finite impulse response filter comprising:
an input stage including a most significant bit portion receiving a most significant bit sum input and a most significant bit carry input, and a least significant bit portion receiving a least significant bit sum input and a least significant bit carry input;
a first multiplier multiplying a first coefficient and a first weight and outputting a result of the multiplication as a most significant bit pair and a least significant bit pair;
a carry-save adder stage including:
a most significant bit portion-coupled to the first multiplier and receiving the most significant bit pair from the first multiplier, coupled to the most significant bit portion of the input stage and receiving the most significant bit sum and most significant bit carry inputs, and outputting a most significant bit sum and a most significant bit carry;
and
a least significant bit portion coupled to the first multiplier and receiving the least significant bit pair from the first multiplier, coupled to the least significant bit portion of the input stage and receiving the least significant bit sum and carry inputs, and outputting a least significant bit sum and a least significant bit carry;
a second multiplier multiplying a second coefficient and a second weight and outputting a result of the multiplication as a most significant bit pair and a least significant bit pair;
and
a carry-save adder/carry-propagate adder stage outputting a most significant bit result and a least significant bit result and including:
a most significant bit portion coupled to the second multiplier and receiving the most significant bit pair from the second multiplier, coupled to the most significant bit portion of the carry-save adder stage and receiving the most significant bit sum and carry output from the carry-save adder stage, and outputting the most significant bit result;
and
a least significant bit portion coupled to the second multiplier and receiving the least significant bit pair from the second multiplier, coupled to the least significant bit portion of the carry-save adder stage and receiving the least significant bit sum and carry outputs from the carry-save adder stage, and
outputting the least significant bit result.

11 more elements

An apparatus comprising:

a finite impulse response filter, comprising:
an input stage including a most significant bit portion receiving a most significant bit sum input and a most significant bit carry input, and an least significant bit portion receiving a least significant bit input;
a first multiplier multiplying a first coefficient and a first weight and outputting a result of the multiplication as a most significant bit pair and a least significant bit pair;
a first carry-save adder/carry propagate adder stage including:
a most significant bit portion coupled to the first multiplier and receiving the most significant bit pair from the first multiplier, coupled to the most significant bit portion of the input stage and receiving the most significant bit sum, most significant bit carry and least significant bit inputs from the input stage, and outputting a most significant bit sum and a most significant bit carry;
and
a least significant bit portion coupled to the first multiplier and receiving the least significant bit pair from the first multiplier, coupled to the least significant bit portion of the input stage and receiving the least significant bit input from the input stage, and outputting a least significant bit sum and a least significant bit carry;
a second multiplier multiplying a second coefficient and a second weight and outputting a result of the multiplication as a most significant bit pair and a least significant bit pair;
and
a second carry-save adder/carry-propagate adder stage outputting a most significant bit result and a least significant bit result and including:
a most significant bit portion coupled to the second multiplier and receiving the most significant bit pair from the second multiplier, coupled to the most significant bit portion of the first carry-save adder/carry-propagate adder stage and receiving the most significant bit sum and most significant bit carry output from the first carry-save adder/carry-propagate adder stage, coupled to the least significant bit portion of the first carry-save adder/carry-propagate adder stage and receiving the least significant bit carry output from the first carry-save adder/carry-propagate adder stage, and outputting the most significant bit result;
and
a least significant bit portion coupled to the second multiplier and receiving the least significant bit pair from the Second multiplier, coupled to the least significant bit portion of the first carry-save adder/carry propagate adder stage and receiving the least significant bit sum output from the first carry-save adder/carry propagate adder stage, and outputting the least significant bit result.

10 more elements

Dependencies are inferred from the claim text.