System and method for automated design verification

A method of automatic circuit design verification, comprising the steps of:

• inputting a reference description from a database with a test bench wherein said reference description optionally provides a basis of a functional model;
• identifying a plurality of states and a plurality of transition arcs in at least one member of the collection comprising a design description and said reference description;
• fetching coverage data that describes how much of said design description has already been tested from a coverage database;
• generating with said test generator a set of at least one test vector to test at least one portion of said simulated electronics design that has not yet been covered;
• transmitting with said test generator said set of said test vectors to said test bench to exercise said simulated electronics design;
• modifying with a coverage analysis tool said coverage database to indicate which of said states and of said transition arcs have been tested;
• and
• repeating the generation step if any portion of the simulated electronics design remains untested.