Utilizing a technology-independent system description incorporating a metal layer dependent attribute

A method for designing an electronic circuit to be implemented on an integrated circuit die having plural metal layers, the method comprising:

• a generating step of generating a hardware description language (HDL) description of a system, the HDL description specifying a signal and a selected metal layer for the signal;
• and
• a synthesis step of synthesizing an electronic circuit description of the system from the HDL description of the system generated in said generating step, the electronic circuit description of the system specifying plural electronic components, an interconnection between two of the plural electronic components and further specifying that the interconnection between the two electronic components is to be routed on the selected metal layer,
• wherein the interconnection between the two electronic components corresponds to the signal specified in said generating step.

A method for synthesizing an electronic circuit description of a system from a technology-independent description of the system, said method comprising:

• an input step of inputting a technology-independent description of the system, the technology-independent description specifying a signal and a metal layer attribute for the signal;
• a selecting step of selecting electronic components from a library based on the technology-independent description;
• an interconnection-specifying step of specifying interconnections between the electronic components;
• and
• a metal-layer specifying step of specifying a metal layer for an interconnection corresponding to the signal specified in the technology-independent description based on the metal layer attribute specified in the technology-independent description.

A method for synthesizing an electronic circuit description of a system from a hardware description language (HDL) description of the system, said method comprising:

• an input step of inputting the HDL description of the system, the HDL description specifying a signal and a metal layer attribute for the signal;
• a selecting step of selecting electronic components from a library based on the HDL description;
• an interconnection-specifying step of specifying interconnections between the electronic components;
• and
• a metal-layer specifying step of specifying a metal layer for an interconnection corresponding to the signal specified in said input step based on the metal layer attribute specified in the HDL description.

An apparatus for synthesizing an electronic circuit description of a system from a technology-independent description of the system, said apparatus comprising:

• a processor for executing stored program instruction steps;
• and
• a memory connected to the processor for storing the program instruction steps,
• wherein the program instruction steps include:
• (1) an input step to input a technology-independent description of the system, the technology-independent description specifying a signal and a metal layer attribute for the signal;
• (2) a selecting step to select electronic components from a library based on the technology-independent description;
• (3) an interconnection-specifying step to specify interconnections between the electronic components;
• and (4) a metal-layer specifying step to specify a metal layer for an interconnection corresponding to the signal specified in the technology-independent description based on the metal layer attribute specified in the technology-independent description.

An apparatus for synthesizing an electronic circuit description of a system from a hardware description language (HDL) description of the system, said apparatus comprising:

• a processor for executing stored program instruction steps;
• and
• a memory connected to the processor for storing the program instruction steps,
• wherein the program instruction steps include:
• (1) an input step to input the HDL description of the system, the HDL description specifying a signal and a metal layer attribute for the signal;
• (2) a selecting step to select electronic components from a library based on the HDL description;
• (3) an interconnection-specifying step to specify interconnections between the electronic components;
• and (4) a metal-layer specifying step to specify a metal layer for an interconnection corresponding to the signal specified in said input step based on the metal layer attribute specified in the HDL description.

Computer-executable process steps stored on a computer readable medium, said process steps for synthesizing an electronic circuit description of a system from a technology-independent description of the system, said process steps comprising:

• an input step to input a technology-independent description of the system, the technology-independent description specifying a signal and a metal layer attribute for the signal;
• a selecting step to select electronic components from a library based on the technology-independent description;
• an interconnection-specifying step to specify interconnections between the electronic components;
• and
• a metal-layer specifying step to specify a metal layer for an interconnection corresponding to the signal specified in the technology-independent description based on the metal layer attribute specified in the technology-independent description.

Computer-executable process steps stored on a computer readable medium, said process steps for synthesizing an electronic circuit description of a system from a hardware description language (HDL) description of the system, said process steps comprising:

• an input step to input the HDL description of the system, the HDL description specifying a signal and a metal layer attribute for the signal;
• a selecting step to select electronic components from a library based on the HDL description;
• an interconnection-specifying step to specify interconnections between the electronic components;
• and
• a metal-layer specifying step to specify a metal layer for an interconnection corresponding to the signal specified in said input step based on the metal layer attribute specified in the HDL description.