Dual mode clock alignment and distribution device

A dual mode PCI adapter device for interfacing between a PCI bus and a PCI device, comprising:

• a clock buffer cell arranged to receive a first clock, the clock buffer cell delaying the first clock;
• a PLL arranged to receive the delayed first clock from the clock buffer, the PLL being configured to output a second clock;
• a first set and a second set of buffers arranged to receive the delayed first clock from the clock buffer cell for operating in a PCI mode, the first and second sets of buffers being further arranged to receive the second clock from the PLL for operating in a PCI-X mode, wherein the first set of buffers delays the received clock by a first delay to output a third clock and the second set of buffers delays the received clock by a second delay to output a fourth clock, and wherein the first, third, and fourth clocks are all aligned when operating in the PCI-X mode;
• a core logic having a set of flip-flops and being arranged to receive and output data and address from the PCI bus in response to the third clock;
• and
• an output flip-flop coupled to receive the data from the logic circuit to output the data to the PCI device in response to the fourth clock.

A dual mode clock alignment and distribution device, comprising:

• a clock buffer cell arranged to receive a first clock, the clock buffer cell being adapted to delay the first clock;
• a PLL arranged to receive the delayed first clock from the clock buffer, the PLL being configured to output a second clock;
• and
• a first set and a second set of buffers arranged to receive the delayed first clock from the clock buffer cell for operating in a first clock mode, the first and second sets of buffers being further arranged to receive the second clock from the PLL for operating in a second clock mode, wherein the first set of buffers delays the received clock by a first delay to output a third clock and the second set of buffers delays the delayed clock by a second delay to output a fourth clock, and wherein the first, third, and fourth clocks are all aligned when operating in the second clock mode;
• a logic circuit having a set of flip-flops and being arranged to receive and output data and address in response to the third clock;
• and
• a set of I/O cells coupled to receive the data and address from the logic circuit to output the data and address in response to the fourth clock.