Digital PLL circuit

A digital PLL circuit comprising:

• a variable-frequency ring oscillator configured to generate an output signal;
• a frequency divider configured to frequency-divide the output signal of said ring oscillator and generate a frequency-divided output signal;
• a phase comparator configured to compare the frequency-divided output signal of said frequency divider with a phase reference signal and generate a comparison output signal;
• and
• a control signal generator configured to generate a control signal corresponding to the comparison output signal of said phase comparator and supply the control signal to said ring oscillator,
• wherein said ring oscillator includes:
• a plurality of delay circuits connected in a multistage,
• a multiplexer configured to select one of output signals of said delay circuits, determine the number of stages of said delay circuits and generate an output signal corresponding to the determined number of stages,
• an inverting delay circuit configured to invert the output signal of said multiplexer,
• a variable capacitor including a plurality of capacitor elements selectively connected to change a value of capacitance, and
• a control circuit configured to refer to correction information and control said multiplexer for selection of said delay circuits and said variable capacitor for connection of the capacitor elements of said variable capacitor, and
• wherein the correction information indicates an optimum number of capacitor elements obtained during shifting from the stage of the delay circuits before the transient to the stage of the delay circuits after the transient.

A digital PLL circuit comprising:

• a variable-frequency ring oscillator configured to generate an output signal;
• a frequency divider configured to frequency-divide the output signal of said ring oscillator and generate a frequency-divided output signal;
• a phase comparator configured to compare the frequency-divided output signal of said frequency divider with a phase reference signal and generate a comparison output signal;
• and
• a control signal generator configured to generate a control signal corresponding to the comparison output signal of said phase comparator and supply the control signal to said ring oscillator,
• wherein said ring oscillator includes:
• a plurality of delay circuits connected in a multistage,
• a multiplexer configured to select one of output signals of said delay circuits, determine the number of stages of said delay circuits and generate an output signal corresponding to the determined number of stages,
• an inverting delay circuit configured to invert the output signal of said multiplexer,
• a variable capacitor including a plurality of capacitor elements selectively connected to change a value of capacitance, and
• a control circuit configured to refer to correction information and control said multiplexer for selection of said delay circuits and said variable capacitor for connection of the capacitor elements of said variable capacitor, and
• wherein said delay circuits and said variable capacitor are so constructed that the length of delay time when the value of capacitance of the variable capacitor is brought close to the maximum value at a certain number of stages of delay circuits overlaps with the length of delay time when the value of capacitance of the variable capacitor is brought close to the minimum value in a case where the number of stages of delay circuits is increased by one.

A digital PLL circuit comprising:

• a variable-frequency ring oscillator configured to generate an output signal;
• a frequency divider configured to frequency-divide the output signal of said ring oscillator and generate a frequency-divided output signal;
• a phase comparator configured to compare the frequency-divided output signal of said frequency divider with a phase reference signal and generate a comparison output signal;
• and
• a control signal generator configured to generate a control signal corresponding to the comparison output signal of said Phase comparator and supply the control signal to said ring oscillator,
• wherein said ring oscillator includes:
• a plurality of delay circuits connected in a multistage,
• a multiplexer configured to select one of output signals of said delay circuits, determine the number of stages of said delay circuits and generate an output signal corresponding to the determined number of stages,
• an inverting delay circuit configured to invert the output signal of said multiplexer,
• a variable capacitor including a plurality of capacitor elements selectively connected to change a value of capacitance, and
• a control circuit configured to refer to correction information and control said multiplexer for selection of said delay circuits and said variable capacitor for connection of the capacitor elements of said variable capacitor, and
• wherein said delay circuits are so constructed that a certain number of stages of delay circuits selected by said multiplexer and its adjacent number of stages of delay circuits have an overlap area where the length of d the delay time characteristic of the former overlaps with the length of delay time in the delay time characteristic of the latter.

A digital PLL circuit comprising:

• a ring oscillator comprising a plurality of delay circuits connected in a multistage, a multiplexer configured to select one of output signals of said delay circuits and determine the number of stages of said delay circuits, a first inverter circuit receiving an output signal of said multiplexer, an offset delay circuit configured to output a delay signal obtained by delaying the output signal of said first inverter circuit by an offset delay time and feed back the delay signal to a first stage circuit of said delay circuits, a variable capacitor connected between an input node of said first stage circuit and a ground node, a second inverter circuit connected to an output of said multiplexer, and a logical gate connected to an output of said second inverter circuit and configured to respond to an external correction enable signal;
• a control circuit connected to an output of said second inverter circuit and configured to control the number of stages of the delay circuits and a capacitance value of said variable capacitor;
• a frequency divider circuit configured to frequency-divide an output signal of said ring oscillator;
• a phase comparator circuit configured to compare a frequency-divided signal of said frequency divider circuit with a phase reference signal;
• and
• a control signal generator circuit configured to generate a control signal corresponding to a phase comparison output signal of said phase comparator circuit and input it to said control circuit.