Spread spectrum clocking of digital signals

Apparatus for reducing electromagnetic interference of a system requiring a clock signal, the circuit comprising:

• a clock circuit configured to generate the clock signal;
• a noise generator configured to generate a noise signal;
• a logic circuit that combines the clock signal and the noise signal according to a function to generate a spread spectrum clock signal, the spread spectrum clock signal comprising a substantially random waveform, wherein the logic circuit includes a first output terminal and a second output terminal;
• one or more clock distribution buses for distributing the spread spectrum clock signal to one or more locations associated with the system, the one or more clock distribution buses comprising first and second channels establishing a communications link between the logic circuit and the one or more locations, the first channel and second channel coupled to the first output terminal and the second output terminal, respectively, of the logic circuit;
• a clock recovery circuit for recovering the clock signal from the spread spectrum clock signal at the one or more locations;
• and
• a reference circuit for generating a reference voltage,
• wherein the logic circuit comprises:
• a first switch having first and second input terminals coupled to receive the clock signal and the reference voltage, respectively, and an output terminal coupled to the first channel, the first switch alternately coupling the first channel between the clock signal and the reference voltage in response to the noise signal;
• and
• a second switch having first and second input terminals coupled to receive the clock signal and the reference voltage, respectively, and an output terminal coupled to the second channel, the second switch alternately coupling the second channel between the clock signal and the reference voltage in response to the noise signal.

A method for reducing the electromagnetic interference (EMI) of a clock signal to be distributed via one or more buses to a receiving component of an electronic device, the method comprising:

• generating a noise signal;
• combining the clock signal with the noise signal to generate a spread spectrum clock signal;
• distributing the spread spectrum clock signal to the receiving component via the one or more buses;
• and
• recovering the clock signal from the spread spectrum clock signal and the noise signal,
• wherein the step of combining comprises alternately coupling of the clock signal between first and second communication channels according to the logic state of the noise signal.

Apparatus for reducing electromagnetic interference of a system requiring a clock signal, the circuit comprising:

• a clock circuit configured to generate a periodic clock signal;
• a first noise generator configured to generate a first noise signal, the first noise generator including a reset port for resetting the first noise generator to a predefined starting state in response to a synchronization signal;
• a logic circuit that combines the periodic clock signal and the first noise signal according to a function to generate a spread spectrum clock signal, the spread spectrum clock signal comprising a substantially random waveform;
• a single clock distribution bus configured to distribute the spread spectrum clock signal to one or more locations associated with the system;
• and
• a clock recovery circuit configured to recover the periodic clock signal from the spread spectrum clock signal at the one or more locations, the clock recovery circuit including a second noise generator for generating a second noise signal, wherein the second noise generator is functionally equivalent to the first noise generator and includes a reset port for resetting the second noise generator to the predefined starting state in response to the synchronization signal,
• wherein
• the first noise generator includes an input to receive a rising edge of the periodic clock signal;
• the second noise generator includes an input to receive a falling edge of the recovered periodic clock signal;
• and
• the logic circuit includes an exclusive-OR logic gate having first and second input terminals coupled to the clock circuit and an output terminal of the first noise generator, respectively, and having an output terminal coupled to the single clock distribution bus.