Method, system and apparatus for calibrating a pulse position modulation (PPM) decoder to a PPM signal

A method of calibrating a pulse position modulation (PPM) decoder to a PPM signal, said method comprising the steps of:

• a) loading 016 (0000b) in a bit window counter;
• b) loading 516 (0101b) in a bit down counter when a first PPM pulse is detected;
• c) decrementing the bit down counter on each clock pulse;
• d) determining when a second PPM pulse is detected, wherein
• if the second PPM pulse is detected then going to step I), and
• if the second PPM pulse is not detected then going to step e);
• e) determining when the bit down counter is equal to 016 (0000b), wherein
• if the bit down counter is not equal to 016 (0000b) then returning to step c), and
• if the bit down counter is equal to 016 (0000b) then going to step f);
• f) reloading the bit down counter;
• g) incrementing the bit window counter;
• h) determining if the bit window counter has overflowed, wherein
• if the bit window counter has overflowed then returning to step a), and
• if no overflow, then returning to step c);
• i) determining if the bit window counter is from 516 (0101b) to 716 (0111b), wherein
• if the bit window counter is not from 516 (0101b) to 716 (0111b) then determining if the bit window counter is from 116 (0001b) to 216 (0010b), wherein
• if the bit window counter is from 116 (0001b) to 216 (0010b)
• then executing a fast read command decode, and
• if not then returning to step a),
• if the bit window counter is from 516 (0101b) to 716 (0111b) then continuing to step j);
• j) loading 616 (0110b) into the bit window counter;
• k) loading 516 (0101b) into the bit down counter;
• l) determining when a calibration start function is true, then
• l1) incrementing a calibration counter on each clock pulse,
• l2) determining if a third PPM pulse is detected, wherein
• if the third PPM pulse is detected then stopping the calibration counter and going to step t), and
• if not detected then going to step m)
• m) determining if the calibration counter is equal to 2F16 (0010 1111b), wherein
• if the calibration counter is not equal to 2F16 (0010 1111b) then
• going to step l1), and
• if equal then stopping the calibration counter and going to step o);
• n) decrementing the bit down counter on each clock pulse;
• o) determining if the third PPM pulse is detected, wherein
• if the third PPM pulse is detected then going to step t), and
• if not detected then going to step p1);
• p1) determining if the bit down counter is equal to 016 (0000b), wherein
• if the bit down counter is not equal to 016 (0000b) then returning to
• step n), and
• if equal to 016 (0000b), then going to step q);
• p2) reloading the bit down counter;
• q) determining if the bit window counter is equal to F16 (1111b), wherein
• if the bit window counter is equal to F16 (1111b) then returning to step a), and
• if not equal then going to step s);
• r) incrementing the bit window counter then returning to step n);
• s) determining if the bit window counter is from C16 (1100b) to F16 (1111b), wherein
• if the bit window counter is not from C16 (1100b) to F16 (1111b) then going to step a), and
• if the bit window counter is from C16 (1100b) to F16 (1111b) then going to step u);
• t) recognizing a PPM code violating calibration symbol;
• u) loading E16 (1110b) into the bit window counter;
• v) loading 516 (0101b) into the bit down counter;
• w) loading a value in the calibration counter into the calibration code register;
• x) decrementing the bit down counter on each clock pulse;
• y) determining when a fourth PPM pulse is detected, wherein
• if the fourth PPM pulse is detected then returning to step a), and
• if the fourth PPM pulse is not detected then going to step aa);
• z) determining when the bit down counter is equal to 016 (0000b), wherein
• if the bit down counter is not equal to 016 (0000b) then returning to
• step y), and
• if equal to 016 (0000b) then going to step bb);
• aa) reloading the bit down counter;
• bb) incrementing the bit window counter;
• cc) determining when the bit window counter is equal to 016 (0000b), wherein
• if the bit window counter is not equal to 016 (0000b) then returning to step y), and
• if equal to 016 (0000b) then going to step ee);
• dd) starting PPM symbol reception;
• ee) decrementing the bit down counter on each clock pulse;
• ff) determining when another PPM pulse is detected, wherein
• if the another PPM pulse is detected then going to step kk);
• and
• if the another PPM pulse is not detected then going to step hh);
• gg) determining when the bit down counter is equal to 016 (0000b), wherein
• if the bit down counter is not equal to 016 (0000b) then returning to step ff), and
• if equal to 016 (0000b) then going to step ii);
• hh) reloading the bit down counter;
• ii) incrementing the bit window counter then returning to step ff);
• jj) loading 516 (0101b) into the bit down counter;
• and
• kk) decoding a symbol value with the bit window counter.

A radio frequency identification (RFID) tag system having a pulse position modulation (PPM) decoder which calibrates to a received PPM signal, said RFID tag system comprising:

• a PPM modulation detector;
• an internal oscillator;
• a PPM decoder having inputs connected to the PPM modulation detector and the internal oscillator, and an output having symbol data, wherein the PPM decoder is adapted for receiving a detected PPM signal from the PPM modulation detector and clock timing from the internal oscillator, said PPM decoder comprising:
• a synchronizer;
• a PPM decoder state machine
• a calibration/reload function
• a bit down counter;
• a bit window counter;
• and
• a symbol register having a data symbol output,
• wherein:
• the synchronizer has a first input adapted to receive the detected PPM signal, a second input connected to the internal oscillator, and an output connected to a first input of the PPM decoder state machine and a first input of the symbol register;
• the PPM decoder state machine has a second input connected to the internal oscillator and a first output connected to a first input of the calibration/reload function, a second output connected to a second input of the bit down counter and a third output connected to a second input of the bit window counter;
• the calibration/reload function has a second input connected to the internal oscillator and an output connected to a first input of the bit down counter;
• the bit down counter has a third input connected to the internal oscillator and an output connected to a first input of the bit window counter;
• the bit window counter has a third input connected to the internal oscillator, a first output connected to a second input of the symbol register, and a second output connected to a third input of the PPM decoder state machine;
• and
• the symbol register has an output comprising the symbol data.