Data communication circuit having FIFO buffer with frame-in-FIFO generator

A data communication circuit for buffering data, which is divided into multiple-bit data frames, the circuit comprising:

• a data routing circuit;
• a data interface;
• and
• a transmit first-in-first-out (“FIFO”) buffer and a receive FIFO buffer, wherein each buffer is operatively coupled between the data routing circuit and the data interface and comprises:
• a write port comprising a data input, an end-of-frame input and a write control input;
• a read port comprising a data output, an end-of-frame output and a read control input;
• a plurality of storage locations for storing data bits received on the data input;
• a write end-of-frame counter coupled to the write port and having a write count output, which increments according to a Grey Code as a function of the end-of-frame input and the write control input;
• a read end-of-frame counter coupled to the read port and having a read count output, which increments according to a Grey Code as a function of the end-of-frame output and the read control input;
• and
• a comparator having first compare input coupled to the write count output, a second compare input coupled to the read count output and a compare output indicating whether there is a data frame stored in the plurality of storage locations.

A method of buffering multiple-bit data frames in a data communication system, wherein each data frame has a beginning and an end, the method comprising:

• storing successive portions of successive ones of the data frames in a first-in-first-out (FIFO) buffer, wherein each successive portion includes an end-of-frame flag, which is asserted when the portion being stored includes the end of that data frame;
• incrementing a grey-coded write count as each of the asserted end-of-frame flags is stored in the FIFO;
• reading the successive data frame portions from the FIFO buffer;
• incrementing a grey-coded read count as each of the data frame portions that have an asserted end-of-frame flag is read from the FIFO;
• and
• controlling the step of reading as a function of a comparison of the write count and the read count.